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june 2013 i ? 2013 microsemi corporation igloo nano low power flash fpgas with flash*freeze technology features and benefits low power ? nanopower consumption?industry?s lowest power ? 1.2 v to 1.5 v core voltage support for low power ? supports single-voltage system operation ? low power active fpga operation ? flash*freeze technology enables ultra-low power consumption while maintaining fpga content ? easy entry to / exit from ultra-low power flash*freeze mode small footprint packages ? as small as 3x3 mm in size wide range of features ? 10,000 to 250,000 system gates ? up to 36 kbits of true dual-port sram ? up to 71 user i/os reprogrammable flash technology ? 130-nm, 7-layer metal, flash-based cmos process ? instant on level 0 support ? single-chip solution ? retains programmed design when powered off ? 250 mhz (1.5 v systems) and 160 mhz (1.2 v systems) system performance in-system programming (isp) and security ? isp using on-chip 128-bit advanced encryption standard (aes) decryption via jt ag (ieee 1532?compliant) ? flashlock ? designed to secure fpga contents ?1.2v programming high-performance routing hierarchy ? segmented, hierarchical routing and clock structure advanced i/os ? 1.2 v, 1.5 v, 1.8 v, 2.5 v, and 3.3 v mixed-voltage operation ? bank-selectable i/o voltages?up to 4 banks per chip ? single-ended i/o standards: lvttl, lvcmos 3.3v/2.5v/1.8v/1.5v/1.2v ? wide range power supply voltage support per jesd8-b, allowing i/os to operate from 2.7 v to 3.6 v ? wide range power supply voltage support per jesd8-12, allowing i/os to operate from 1.14 v to 1.575 v ? i/o registers on input, output, and enable paths ? selectable schmitt trigger inputs ? hot-swappable and cold-sparing i/os ? programmable output slew rate and drive strength ? weak pull-up/-down ? ieee 1149.1 (jtag) boundary scan test ? pin-compatible packages across the igloo ? family clock conditioning circuit (ccc) and pll ? ? up to six ccc blocks, one with an integrated pll ? configurable phase shift, multiply/divide, delay capabilities, and external feedback ? wide input frequency range (1.5 mhz up to 250 mhz) embedded memory ? 1 kbit of flashrom user nonvolatile memory ? srams and fifos with variable-aspect-ratio 4,608-bit ram blocks (1, 2, 4, 9, and 18 organizations) ? ? true dual-port sram (except 18 organization) ? enhanced commercial temperature range ? tj = -20c to +85c ? agln030 and smaller devices do not support this feature. igloo nano devices agln010 agln015 1 agln020 agln060 agln125 agln250 igloo nano-z devices 1 agln030z 1 agln060z 1 agln125z 1 agln250z 1 system gates 10,000 15,000 20,000 30,000 60,000 125,000 250,000 typical equivalent macrocells 86 128 172 256 512 1,024 2,048 versatiles (d-flip-flops) 260 384 520 768 1,536 3,072 6,144 flash*freeze mode (typical, w) 2 4 4 5 10 16 24 ram kbits (1,024 bits) 2 ? ? ? ? 18 36 36 4,608-bit blocks 2 ??? ? 4 8 8 flashrom kbits (1,024 bits) 1 1 1 1 1 1 1 secure (aes) isp 2 ??? ? yesyesyes integrated pll in cccs 2,3 ??? ? 1 1 1 versanet globals 4 4 4 6 18 18 18 i/o banks 2 3 3 2 2 2 4 maximum user i/os (packaged device) 34 49 52 77 71 71 68 maximum user i/os (known good die) 34 ? 52 83 71 71 68 package pins uc/cs qfn vqfp uc36 qn48 qn68 uc81, cs81 qn68 uc81, cs81 qn48, qn68 vq100 cs81 vq100 cs81 vq100 cs81 vq100 notes: 1. not recommended for new designs. 2. agln030 and smaller devices do not support this feature. 3. agln060, agln125, and agln250 in t he cs81 package do not support plls. 4. for higher densities and support of additional features, refer to the igloo and iglooe datasheets. revision 17
ii revision 17 i/os per package igloo nano device status igloo nano devices agln010 agln015 1 agln020 agln060 agln125 agln250 igloo nano-z devices 1 agln030z 1 agln060z 1 agln125z 1 agln250z 1 known good die 34 ? 52 83 71 71 68 uc36 23 ? ? ? ? ? ? qn48 34 ? ? 34 ? ? ? qn68 ? 49 49 49 ? ? ? uc81 ? ? 52 66 ? ? ? cs81 ? ? 52 66 60 60 60 vq100 ? ? ? 77 71 71 68 notes: 1. not recommended for new designs. 2. when considering migrating your design to a lower- or higher-density device, refer to the igloo datasheet and igloo fpga fabric user?s guide to ensure compliance with design and board migration requirements. 3. when the flash*freeze pin is used to directly enable flash*fr eeze mode and not used as a regular i/o, the number of single- ended user i/os available is reduced by one. 4. "g" indicates rohs-compliant packages. refer to "igloo nano ordering information" on page iii for the location of the "g" in the part number. for nano devices, the vq1 00 package is offered in both leaded and rohs-compliant versions. all other packages are rohs-compliant only. table 1 ? igloo nano fpgas package sizes dimensions packages uc36 uc81 cs81 qn48 qn68 vq100 length width (mm\mm) 3 x 3 4 x 4 5 x 5 6 x 6 8 x 8 14 x 14 nominal area (mm 2 ) 9 16 36 36 64 196 pitch (mm) 0.4 0.4 0.5 0.4 0.4 0.5 height (mm) 0.80 0.80 0.80 0.90 0.90 1.20 igloo nano devices status igloo nano-z devices status agln010 production agln015 not recommended for new designs. agln020 production agln030z not recommended for new designs. agln060 production agln060z not recommended for new designs. agln125 production agln125z not recommended for new designs. agln250 production agln250z not recommended for new designs.
igloo nano low power flash fpgas revision 17 iii igloo nano ordering information devices not recommended for new designs agln015, agln030z, agln060z, agln125z, and ag ln250z are not recommended for new designs. device marking microsemi normally topside marks the full ordering part number on each device. there are some exceptions to this, such as some of the z feature grade nano devices, the v2 designator for igloo devices, and packages where space is physically limited. packages that have limited characters available ar e uc36, uc81, cs81, qn48, qn68, and qfn132 . on these specific packages, a subset of the device marking will be used that includes the required legal information and as much of the pa rt number as allowed by chara cter limitation of the device. in this case, devices will have a trunc ated device marking and may exclude the applications markings, such as the i designator for industrial devices or the es designator for engineering samples. notes: 1. z-feature grade devices agln 060z, agln125z, and agln250z do not support the enhanced nano featur es of schmitt trigger input, bus hold (hold previous i/o state in flash*freeze mode), cold-sparing, hot-swap i/o capability and 1.2 v programming. the agln030 z feature grade does not suppo rt schmitt trigger input, bus hold an d 1.2 v programming. for the vq100, cs81, uc81, qn68, and qn48 packages, the z feature grade and the n part number are not marked on the device. z feature grade devices are not recommended for new designs. 2. agln030 is available in the z feature grade only. 3. marking information: igloo nano v2 devices do not have a v2 marking, but igloo nano v5 devices are marked with a v5 designator. agln010 = 10,000 system gates agln015 = 15,000 system gates (agln015 is not recommended for new designs) agln020 = 20,000 system gates agln030 = 30,000 system gates agln060 = 60,000 system gates agln125 = 125,000 system gates agln250 = 250,000 system gates blank = standard z = nano devices without enhanced features 1 supply voltage 2 = 1.2 v to 1.5 v 5 = 1.5 v only agln250 v2 z vq _ part number igloo nano devices package type vq = very thin quad flat pack (0.5 mm pitch) dielot = known good die qn = quad flat pack no leads (0.4 mm and 0.5 mm pitches) 100 i y package lead count g lead-free packaging application (temperature range) blank = enhanced commercial ( ? 20c to +85c junction temperature) i = industrial ( ? 40c to +100c junction temperature) blank = standard packaging g= rohs-compliant packaging pp = pre-production es = engineering sample (room temperature only) cs = chip scale package (0.5 mm pitch) uc = micro chip scale package (0.4 mm pitch) security feature y = device includes license to implement ip based on the cryptography research, inc. (cri) patent portfolio blank = device does not include license to implement ip based on the cryptography research, inc. (cri) patent portfolio
iv revision 17 figure 1 shows an example of device marking based on the agl030v5 -ucg81. the actual mark will vary by the device/package combination ordered. igloo nano products available in the z feature grade temperature grade offerings contact your local microsemi representative for device availability: http://www.microsemi.com /soc/contact/default.aspx . figure 1 ? example of device marking fo r small form factor packages igloo nano-z devices agln030z* agln060z* agln125z* agln250z* packages qn48 ? ? ? qn68 ? ? ? uc81 ? ? ? cs81 cs81 cs81 cs81 vq100 vq100 vq100 vq100 note: * not recommended for new designs. package agln010 agln015 * agln020 agln060 agln125 agln250 agln030z * agln060z * agln125z * agln250z * uc36 c, i?????? qn48 c, i ? ? c, i ? ? ? qn68 ? c, i c, i c, i ? ? ? uc81 ? ? c, i c, i ? ? ? cs81 ? ? c, i c, i c, i c, i c, i vq100 ? ? ? c, i c, i c, i c, i note: * not recommended for new designs. c = enhanced commercial temperature range: ?20c to +85c junction temperature i = industrial temperature range: ?4 0c to +100c junction temperature actelxxx agl030yww ucg81xxxx xxxxxxxx country of origin date code customer mark (if applicable) device name (six characters) package wafer lot #
igloo nano low power flash fpgas revision 17 v table of contents igloo nano device overview general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 igloo nano dc and switching characteristics general specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 calculating power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 user i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 versatile characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57 global resource characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63 clock conditioning circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70 embedded sram and fifo characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-73 embedded flashrom characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-87 jtag 1532 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-88 pin descriptions supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 user pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 jtag pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 special function pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 package pin assignments uc36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 uc81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 cs81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 qn48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 qn68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 vq100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 datasheet information list of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 datasheet categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 safety critical, life support, and high-reliability applications policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

revision 17 1-1 1 ? igloo nano device overview general description the igloo family of flash fpgas, based on a 130-nm flash process, offers the lowest power fpga, a single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced features. the flash*freeze technology used in igloo nano devices enables entering and exiting an ultra-low power mode that consumes nanopower while retaining sram and register data. flash*freeze technology simplifies power management through i/o and clock management with rapid recovery to operation mode. the low power active capability (static idle) allo ws for ultra-low power c onsumption while the igloo nano device is completely functional in the system. this allows the igloo nano device to control system power management based on external inputs (e.g., scanning for keyboard stimulus) while consuming minimal power. nonvolatile flash technology gives igloo nano devic es the advantage of being a secure, low power, single-chip solution that is instant on. the iglo o nano device is reprogrammable and offers time-to- market benefits at an asic-level unit cost. these features e nable designers to create high -density systems using existing asic or fpga design flows and tools. igloo nano devices offer 1 kbit of on-chip, reprogra mmable, nonvolatile flashrom storage as well as clock conditioning circuitry based on an integrated ph ase-locked loop (pll). the agln030 and smaller devices have no pll or ram support. igloo nano devices have up to 250 k system gates, supported with up to 36 kbits of true dual-port sram and up to 71 user i/os. igloo nano devices increase the breadth of the igloo product line by adding new features and packages for greater customer value in high volume consumer, portable, and battery-backed markets. features such as smaller footprint packages designe d with two-layer pcbs in mind, power consumption measured in nanopower, schmitt trigger, and bus hol d (hold previous i/o state in flash*freeze mode) functionality make these devices ideal for deployment in applications that require high levels of flexibility and low cost. flash*freeze technology the igloo nano device offers unique flash*freeze technology, allowing the device to enter and exit ultra-low power flash*freeze mode. igloo nano devices do not need additional components to turn off i/os or clocks while retaining the design inform ation, sram content, and registers. flash*freeze technology is combined wi th in-system programmability, which enables users to quickly and easily upgrade and update their designs in the final stages of manufacturing or in the field. the ability of igloo nano v2 devices to support a wide range of core vo ltage (1.2 v to 1.5 v) allows further reduction in power consumption, thus achievi ng the lowest total system power. during flash*freeze mode, each i/o can be set to the following configurations: hold previous state, tristate, high, or low. the availability of low power modes, combined with reprogrammability, a single-chip and single-voltage solution, and small-footprint pack ages make igloo nano devices the best fit for portable electronics.
igloo nano device overview 1-2 revision 17 flash advantages low power flash-based igloo nano devices exhibit power characte ristics similar to those of an asic, making them an ideal choice for power-sensitive applications. igloo nano devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many fpgas. igloo nano devices also have low dynamic power co nsumption to further maximize power savings; power is reduced even further by the use of a 1.2 v core voltage. low dynamic power consumption, combined with low static power consumption and flash*freeze technology, gives the ig loo nano device the lowest total system power offered by any fpga. security nonvolatile, flash-based igloo nano devices do not require a boot prom, so there is no vulnerable external bitstream that can be easily copied. igloo nano devices incorporate flashlock, which provides a unique combination of reprogrammability and desi gn security without external overhead, advantages that only an fpga with nonvolatile flash programming can offer. igloo nano devices utilize a 128-bit flash-based lo ck and a separate aes key to provide the highest level of security in the fpga industry for prog rammed intellectual property and configuration data. in addition, all flashrom data in igloo nano device s can be encrypted prior to loading, using the industry-leading aes-128 (fips192) bit block ci pher encryption st andard. aes was adopted by the national institute of standards and technology (n ist) in 2000 and replaces the 1977 des standard. igloo nano devices have a built-in aes decryption engine and a flash-based aes key that make them the most comprehensive programmable logic device security solution available today. igloo nano devices with aes-based security prov ide a high level of protection fo r remote field u pdates over public networks such as the internet, and are designed to ensure that valuable ip remains out of the hands of system overbuilders, system cloners, and ip thieves. security, built into the fpga fabric, is an inherent component of igloo nano devices. the flash cells are located beneath seven metal layers, and many devi ce design and layout techniques have been used to make invasive attacks extremely di fficult. igloo nano devices, with fl ashlock and aes security, are unique in being highly resi stant to both invasive and noninvasive attacks. your valuable ip is protected with industry-standard security, making remote isp possible. an igloo nano device provides the best available security for programmable logic designs. single chip flash-based fpgas store their configuration informati on in on-chip flash cells. once programmed, the configuration data is an inherent part of the fpga st ructure, and no external configuration data needs to be loaded at system power-up (un like sram-based fpgas). theref ore, flash-based igloo nano fpgas do not require system configuration compo nents such as eeproms or microcontrollers to load device configuration data. this reduces bill-of-materi als costs and pcb area, and increases security and system reliability. instant on microsemi flash-based iglo o nano devices support level 0 of the instant on classification standard. this feature helps in system component initializ ation, execution of critic al tasks before the processor wakes up, setup and configuration of memory blo cks, clock generation, and bus activity management. the instant on feature of flash- based igloo nano devices greatly simplifies total system design and reduces total system cost, often eliminating the n eed for cplds and clock generation plls. in addition, glitches and brownouts in system power will not co rrupt the igloo nano device 's flash configuration, and unlike sram-based fpgas, the device will not have to be reloaded when system power is restored. this enables the reduction or complete removal of the configuration prom, expensive voltage monitor, brownout detection, and clock generator device s from the pcb design. flash-based igloo nano devices simplify total system design and reduce cost and des ign risk while increasin g system reliability and improving system initialization time. igloo nano flash fpgas enable the user to quickly enter and exit flash*freeze mode. this is done almost instantly (within 1 s) and the device retains configuration and data in registers and ram. unlike sram-based fpgas, the device does not need to reload configuration and design state from external memory components; instead it retains all necessary information to resume operation immediately.
igloo nano low power flash fpgas revision 17 1-3 reduced cost of ownership advantages to the designer extend beyond low unit cost, performance, and ease of use. unlike sram-based fpgas, flash-based igloo nano devices allow all functionality to be instant on; no external boot prom is required. on-board securi ty mechanisms prevent access to all the programming information and enable secure remote updates of the fpga logic. designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confid ence that valuable intellectual proper ty cannot be compromised or copied. secure isp can be performed using the industry- standard aes algorithm. the igloo nano device architecture mitigates the need for asic migratio n at higher user volumes. this makes igloo nano devices cost-effective asic replacement solutions , especially for applications in the consumer, networking/communications, computing, and avionics markets. with a variety of devices under $1, igloo nano fpgas enable cost-effective implementation of programmable logic and quick time to market. firm-error immunity firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an sram fpga. the energ y of the collision can ch ange the state of the configuration cell and thus change t he logic, routing, or i/o behavior in an unpredictable way. these errors are impossible to prevent in sram fpgas. the consequence of this type of error can be a complete system failur e. firm errors do not exist in the confi guration memory of ig loo nano fl ash-based fpgas. once it is programmed, the flash cell co nfiguration element of igloo nano fpgas cannot be altered by high-energy neutrons and is therefore im mune to them. recoverable (or soft) errors occur in the user data sram of all fpga devices. these can easily be mitigated by using error detection and correction (edac) circuitry built into the fpga fabric. advanced flash technology the igloo nano device offers many benefits, including nonvolatilit y and reprogrammability, through an advanced flash-based, 130-nm lvcmos process with seven layers of metal. standard cmos design techniques are used to implement logic and contro l functions. the combination of fine granularity, enhanced flexible routing resources, and abundant fl ash switches allows for very high logic utilization without compromising device routability or perform ance. logic functions within the device are interconnected through a four-level routing hierarchy. igloo nano fpgas utilize design and process techni ques to minimize power consumption in all modes of operation. advanced architecture the proprietary igloo nano architec ture provides granularity comparable to standard-cell asics. the igloo nano device consists of five distinct and programmable architectural features ( figure 1-3 on page 1-5 to figure 1-4 on page 1-5 ): ? flash*freeze technology ? fpga versatiles ? dedicated flashrom ? dedicated sram/fifo memory ? ? extensive cccs and plls ? ? advanced i/o structure the fpga core consists of a sea of versatiles. each versatile can be configured as a three-input logic function, a d-flip-flop (with or without enable), or a latch by progr amming the appropriate flash switch interconnections. the versatility of the igloo nano core tile as eit her a three-input lookup table (lut) equivalent or a d-flip-flop/latch with enable allows fo r efficient use of the fpga fabric. the versatile capability is unique to the proasic ? family of third-generation-archit ecture flash fpgas. versatiles are connected with any of the four leve ls of routing hierarchy. flash swit ches are distributed throughout the device to provide nonvolatile, reconfigurable inte rconnect programming. maximum core utilization is possible for virtually any design. ? the agln030 and smaller devices do not support pll or sram.
igloo nano device overview 1-4 revision 17 note: *bank 0 for the agln030 device figure 1-1 ? igloo device architecture overvi ew with two i/o banks and no ram (agln010 and agln030) figure 1-2 ? igloo device architecture overview with three i/o banks and no ram (agln015 and agln020) versatile i/os user nonvolatile flashrom flash*freeze technology charge pumps bank 1* bank 1 bank 0 bank 1 ccc-gl ccc-gl versatile i/os user nonvolatile flashrom flash*freeze technology charge pumps bank 1 bank 2 bank 0 bank 1
igloo nano low power flash fpgas revision 17 1-5 . figure 1-3 ? igloo device architecture overview wi th two i/o banks (agln060, agln125) figure 1-4 ? igloo device architecture overview with four i/o banks (agln250) ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os isp aes decryption user nonvolatile flashrom flash*freeze technology charge pumps bank 0 bank 1 bank 1 bank 0 bank 0 bank 1 ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os bank 0 bank 3 bank 3 bank 1 bank 1 bank 2 isp aes decryption user nonvolatile flashrom flash*freeze technology charge pumps
igloo nano device overview 1-6 revision 17 flash*freeze technology the igloo nano device has an ultra-low power static mode, called flash*freeze mode, which retains all sram and register information and can still quickly return to normal operation. flash*freeze technology enables the user to quickly (within 1 s) enter and exit flash*freeze mode by activating the flash*freeze pin while all power supplies are kept at their original values. i/os, global i/os, and clocks can still be driven and can be t oggling without impact on power consumption, and the device retains all core registers, sram information, an d i/o states. i/os can be individually configured to either hold their previous state or be tristated during flash*freeze mode. alternatively, i/os can be set to a specific st ate using weak pull-up or pull-down i/o attribute configuration. no power is cons umed by the i/o banks, clocks, jtag pins, or pll, and the device consumes as little as 2 w in this mode. flash*freeze technology allows the user to switch to active mode on demand, thus simplifying the power management of the device. the flash*freeze pin (active low) can be routed internally to the core to allow the user's logic to decide when it is safe to transition to this mode. refer to figure 1-5 for an illustration of entering/exiting flash*freeze mode. it is also possible to use the fl ash*freeze pin as a regular i/o if flash*freeze mode usage is not planned. versatiles the igloo nano core consists of versatiles , which have been enhanced beyond the proasic plus ? core tiles. the igloo nano versatile supports the following: ? all 3-input logic functions?lut-3 equivalent ? latch with clear or set ? d-flip-flop with clear or set ? enable d-flip-flop with clear or set refer to figure 1-6 for versatile configurations. figure 1-5 ? igloo nano flash*freeze mode figure 1-6 ? versatile configurations igloo nano fpga flash*freeze mode control flash*freeze pin x1 y x2 x3 lut-3 data y clk enable clr d-ff data y clk clr d-ff lut-3 equivalent d-flip-flop with clear or set enable d-flip-flop with clear or set
igloo nano low power flash fpgas revision 17 1-7 user nonvolatile flashrom igloo nano devices have 1 kbit of on-chip, user-accessible, nonvolatile flashrom. the flashrom can be used in diverse system applications: ? internet protocol addressing (wireless or fixed) ? system calibration settings ? device serialization and/or inventory control ? subscription-based business models (for example, set-top boxes) ? secure key storage for secure communications algorithms ? asset management/tracking ? date stamping ? version management the flashrom is written using the standard igloo nano ieee 1532 jtag programming interface. the core can be individually programmed (erased and written), and on-chip aes decryption can be used selectively to securely load data over public networ ks (except in the agln030 and smaller devices), as in security keys stored in the flashrom for a user design. the flashrom can be programmed via the jtag progr amming interface, and its contents can be read back either through the jtag programming interface or via direct fpga core addressing. note that the flashrom can only be programmed from the jtag interface and cannot be programmed from the internal logic array. the flashrom is programmed as 8 banks of 128 bits ; however, reading is performed on a byte-by-byte basis using a synchronous interface. a 7-bit address fr om the fpga core defines which of the 8 banks and which of the 16 bytes within that bank are being read. the three most significant bits (msbs) of the flashrom address determine the bank, and the four least significant bits (lsbs) of the flashrom address define the byte. the igloo nano development software solutions, libero ? system-on-chip (soc) and designer, have extensive support for the flashrom. one such feat ure is auto-generation of sequential programming files for applications requiring a unique serial number in each part. another feature enables the inclusion of static data for system version control. data for the flashrom can be generated quickly and easily using microsemi libero soc and designer software tools. comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing flashrom contents. sram and fifo igloo nano devices (except the agln030 and smaller devices) have embedded sram blocks along their north and south sides. each variable-aspect-rati o sram block is 4,608 bits in size. available memory configurations ar e 25618, 5129, 1k4, 2k2, and 4k1 bits. the in dividual blocks have independent read and write ports that can be confi gured with different bit widths on each port. for example, data can be sent through a 4-bit port and read as a single bitstream. the embedded sram blocks can be initialized via the device jtag port (rom emulation mode) using the ujtag macro (except in the agln030 and smaller devices). in addition, every sram block has an embedded fi fo control unit. the contro l unit allows the sram block to be configured as a synchronous fifo with out using additional core versatiles. the fifo width and depth are programmable. the fifo also feat ures programmable almost empty (aempty) and almost full (afull) flags in addition to the norma l empty and full flags. the embedded fifo control unit contains the counters necessary for generati on of the read and write address pointers. the embedded sram/fifo blocks can be cascaded to create larger configurations. pll and ccc higher density igloo nano devices us ing either the two i/o bank or four i/o bank architectures provide designers with very flexible clock conditioning capa bilities. agln060, agln1 25, and agln250 contain six cccs. one ccc (center west side) has a pll. the agln030 and smaller devices use different cccs in their architecture (ccc-gl). these ccc-gl s contain a global mux but do not have any plls or programmable delays. for devices using the six ccc block architecture, thes e are located at the four corners and the centers of the east and west sides. all six ccc blocks are us able; the four corner cccs and the east ccc allow simple clock delay operations as well as clock spine access.
igloo nano device overview 1-8 revision 17 the inputs of the six ccc blocks are accessible from the fpga core or from dedicated c onnections to the ccc block, which are located near the ccc. the ccc block has these key features: ? wide input frequency range (f in_ccc ) = 1.5 mhz up to 250 mhz ? output frequency range (f out_ccc ) = 0.75 mhz up to 250 mhz ? 2 programmable delay types for clock skew minimization ? clock frequency synthesis (for pll only) additional ccc specifications: ? internal phase shift = 0, 90, 180, and 270. output phase shift depends on the output divider configuration (for pll only). ? output duty cycle = 50% 1.5% or better (for pll only) ? low output jitter: worst case < 2.5% clock per iod peak-to-peak period jitter when single global network used (for pll only) ? maximum acquisition time is 300 s (for pll only) ? exceptional tolerance to input period jitter?allowabl e input jitter is up to 1.5 ns (for pll only) ? four precise phases; maximum misalignment bet ween adjacent phases of 40 ps 250 mhz / f out_ccc (for pll only) global clocking igloo nano devices have ext ensive support for multiple clocking domains. in addition to the ccc and pll support described above, there is a comp rehensive global clock distribution network. each versatile input and output port has access to nine versanets: six chip (main) and three quadrant global networks. the versanets can be driven by the ccc or directly accessed from the core via multiplexers (muxes). the versanets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets. i/os with advanced i/o standards igloo nano fpgas feature a flexible i/o structure, supporting a range of voltages (1.2 v, 1.2 v wide range, 1.5 v, 1.8 v, 2.5 v, 3. 0 v wide range, and 3.3 v). the i/os are organized into banks with two, three, or four banks per device. the configuration of these banks determines the i/o standards supported. each i/o module contains several input, output, and enable registers. these registers allow the implementation of various single-data-rate applicatio ns for all versions of nano devices and double-data- rate applications for the agln0 60, agln125, and agln250 devices. igloo nano devices support lvttl and lvcmos i/o standards, are hot-swappable, and support cold- sparing and schmitt trigger. hot-swap (also called hot-plug, or hot-insertion) is t he operation of hot-insertion or hot-removal of a card in a powered-up system. cold-sparing (also called cold-swap) refers to the ability of a devi ce to leave system data undisturbed when the system is powered up, while the component itself is powered down, or when power supplies are floating. wide range i/o support igloo nano devices support jede c-defined wide range i/o operati on. igloo nano devices support both the jesd8-b specification, cove ring both 3 v and 3.3 v supplies, for an effective operating range of 2.7 v to 3.6 v, and jesd8-12 with its 1.2 v nominal, supporting an effective op erating range of 1.14 v to 1.575 v. wider i/o range means designers can eliminate power supplies or power conditioning components from the board or move to less costly components wit h greater tolerances. wide range eases i/o bank management and provides enhanc ed protection from system voltage sp ikes, while providing the flexibility to easily run custom voltage applications.
igloo nano low power flash fpgas revision 17 1-9 specifying i/o states during programming you can modify the i/o states during programming in fl ashpro. in flashpro, this feature is supported for pdb files generated from designer v8.5 or greater. see the flashpro user?s guide for more information. note: pdb files generated from designer v8.1 to designer v8.4 (including all service packs) have limited display of pin numbers only. 1. load a pdb from the flashpro gui. you must have a pdb loaded to modify the i/o states during programming. 2. from the flashpro gui, click pdb configurat ion. a flashpoint ? pr ogramming file generator window appears. 3. click the specify i/o states during programming button to display the specify i/o states during programming dialog box. 4. sort the pins as desired by clicking any of the column headers to sort the entries by that header. select the i/os you wish to modify ( figure 1-7 on page 1-9 ). 5. set the i/o output state. you can set basic i/o se ttings if you want to use the default i/o settings for your pins, or use custom i/o settings to cust omize the settings for each pin. basic i/o state settings: 1 ? i/o is set to drive out logic high 0 ? i/o is set to drive out logic low last known state ? i/o is set to the last value that was driven out prior to entering the programming mode, and then held at that value during programming z -tri-state: i/o is tristated figure 1-7 ? i/o states during programming window
igloo nano device overview 1-10 revision 17 6. click ok to return to the flashpoint ? programming file generator window. note: i/o states during programming are saved to the adb and resulting programming files after completing programming file generation.
revision 17 2-1 2 ? igloo nano dc and switching characteristics general specifications the z feature grade does not support the enhanced nano features of schmitt trigger input, flash*freeze bus hold (hold previous i/o state in flash*freeze mode), cold-sparing, and hot-swap i/o capability. refer to "igloo nano ordering information" on page iii for more information. operating conditions stresses beyond those listed in ta b l e 2 - 1 may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings are stress ratings only; functional operation of th e device at these or any other conditions beyond those listed under the recommended o perating conditions specified in table 2-2 on page 2-2 is not implied. table 2-1 ? absolute maximum ratings symbol parameter limits units vcc dc core supply voltage ?0.3 to 1.65 v vjtag jtag dc voltage ?0.3 to 3.75 v vpump programming voltage ?0.3 to 3.75 v vccpll analog power supply (pll) ?0.3 to 1.65 v vcci dc i/o buffer supply voltage ?0.3 to 3.75 v vi 1 i/o input voltage ?0.3 v to 3.6 v v t stg 2 storage temperature ?65 to +150 c t j 2 junction temperature +125 c notes: 1. the device should be operated within the limits specified by the datasheet. during transitions, the input signal may undershoot or overshoot according to the limits shown in table 2-4 on page 2-3 . 2. for flash programming and retention maximum limits, refer to table 2-3 on page 2-2 , and for recommended operating limits, refer to table 2-2 on page 2-2 .
igloo nano dc and switching characteristics 2-2 revision 17 table 2-2 ? recommended operating conditions 1 symbol parameter extended commercial industrial units t j junction temperature ?20 to + 85 2 ?40 to +100 2 c vcc 1.5 v dc core supply voltage 3 1.425 to 1.575 1.425 to 1.575 v 1.2 v?1.5 v wide range core voltage 4,5 1.14 to 1.575 1.14 to 1.575 v vjtag jtag dc voltage 1.4 to 3.6 1.4 to 3.6 v vpump 6 programming voltage programming mode 3.15 to 3.45 3.15 to 3.45 v operation 0 to 3.6 0 to 3.6 v vccpll 7 analog power supply (pll) 1.5 v dc core supply voltage 3 1.425 to 1.575 1.425 to 1.575 v 1.2 v?1.5 v wide range core supply voltage 4 1.14 to 1.575 1.14 to 1.575 v vcci and vmv 8,9 1.2 v dc supply voltage 4 1.14 to 1.26 1.14 to 1.26 v 1.2 v dc wide range supply voltage 4 1.14 to 1.575 1.14 to 1.575 v 1.5 v dc supply voltage 1.425 to 1.575 1.425 to 1.575 v 1.8 v dc supply voltage 1.7 to 1.9 1.7 to 1.9 v 2.5 v dc supply voltage 2.3 to 2.7 2.3 to 2.7 v 3.3 v dc supply voltage 3.0 to 3.6 3.0 to 3.6 v 3.3 v dc wide range supply voltage 10 2.7 to 3.6 2.7 to 3.6 v notes: 1. all parameters representing voltages are measured with respect to gnd unless otherwise specified. 2. default junction temperature range in the libero soc software is set to 0c to +70c for commercial, and -40c to +85c for industrial. to ensure targeted reliability standards are met across the full range of junction temperatures, microsemi recommends using custom settings for temperature range before running timing and power analysis tools. for more information regarding custom settings, refer to the new project dialog box in the libero online help. 3. for igloo ? nano v5 devices 4. for igloo nano v2 devices only, operating at vcci ?? vcc 5. igloo nano v5 devices can be programmed with the vcc core voltage at 1.5 v only. igloo nano v2 devices can be programmed with the vcc core voltage at 1.2 v (with flashp ro4 only) or 1.5 v. if you are using flashpro3 and want to do in-system programming using 1. 2 v, please contact the factory. 6. v pump can be left floating during operation (not programming mode). 7. vccpll pins should be tied to vcc pins. see the "pin descriptions" chapter for further information. 8. vmv pins must be connected to the corresponding vcci pins. see the pin descriptions chapter of the igloo nano fpga fabric user?s guide for further information. 9. the ranges given here are for power supplies only. t he recommended input voltage ranges specific to each i/o standard are given in table 2-21 on page 2-19 . vcci should be at the same voltage within a given i/o bank. 10. 3.3 v wide range is compliant to the jesd8-b specification and supports 3.0 v vcci operation. table 2-3 ? flash programming limits ? retention, storage, and operating temperature 1 product grade programming cycles program retention (biased/unbiased) maximum storage temperature t stg (c) 2 maximum operating junction temperature t j (c) 2 commercial 500 20 years 110 100 industrial 500 20 years 110 100 notes: 1. this is a stress rating only; functional operation at any condition other than those indicated is not implied. 2. these limits apply for program/data retention only. refer to table 2-1 on page 2-1 and table 2-2 for device operating conditions and absolute limits.
igloo nano low power flash fpgas revision 17 2-3 i/o power-up and supply voltage thresholds for power-on reset (commercial and industrial) sophisticated power-up management circuitry is desi gned into every igloo nano device. these circuits ensure easy transition from the powered-off state to the powered-up state of the device. the many different supplies can power up in any sequence with mi nimized current spikes or surges. in addition, the i/o will be in a known state through the power-up sequence. the basic principle is shown in figure 2-1 on page 2-4 . there are five regions to consider during power-up. igloo nano i/os are activated only if all of the following three conditions are met: 1. vcc and vcci are above the mi nimum specified trip points ( figure 2-1 and figure 2-2 on page 2-5 ). 2. vcci > vcc ? 0.75 v (typical) 3. chip is in the operating mode. vcci trip point: ramping up (v5 devices): 0.6 v < trip_point_up < 1.2 v ramping down (v5 devices): 0.5 v < trip_point_down < 1.1 v ramping up (v2 devices): 0.75 v < trip_point_up < 1.05 v ramping down (v2 devices): 0.65 v < trip_point_down < 0.95 v vcc trip point: ramping up (v5 devices): 0.6 v < trip_point_up < 1.1 v ramping down (v5 devices): 0.5 v < trip_point_down < 1.0 v ramping up (v2 devices): 0.65 v < trip_point_up < 1.05 v ramping down (v2 devices): 0.55 v < trip_point_down < 0.95 v vcc and vcci ramp-up trip points are about 100 mv hi gher than ramp-down trip points. this specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. note the following: ? during programming, i/os become tristated and weakly pulled up to vcci. ? jtag supply, pll power supplies, and charge pump vpump supply have no influence on i/o behavior. table 2-4 ? overshoot and undershoot limits 1 vcci average vcci?gnd overshoot or undershoot duration as a percentage of clock cycle 2 maximum overshoot/ undershoot 2 2.7 v or less 10% 1.4 v 5% 1.49 v 3 v 10% 1.1 v 5% 1.19 v 3.3 v 10% 0.79 v 5% 0.88 v 3.6 v 10% 0.45 v 5% 0.54 v notes: 1. based on reliability requirements at 85c. 2. the duration is allowed at one out of si x clock cycles. if the overshoot/unders hoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 v.
igloo nano dc and switching characteristics 2-4 revision 17 pll behavior at brownout condition microsemi recommends using monotonic power supplie s or voltage regulators to ensure proper power- up behavior. power ramp-up should be monotonic at least until vcc and vccplx exceed brownout activation levels (see figure 2-1 and figure 2-2 on page 2-5 for more details). when pll power supply voltage and/or vcc levels drop below the vcc brownout levels (0.75 v 0.25 v for v5 devices, and 0.75 v 0.2 v for v2 device s), the pll output lock signal goes low and/or the output clock is lost. refer to the "brownout voltage" section in the "power-up/-down behavior of low power flash devices" chapter of the igloo nano fpga fabric user?s guide for information on clock and lock recovery. internal power-up activation sequence 1. core 2. input buffers 3. output buffers, after 200 ns delay from input buffer activation to make sure the transition from input buffers to output buffers is clean, en sure that there is no path longer than 100 ns from input buffer to output buffer in your design. figure 2-1 ? v5 devices ? i/o state as a function of vcci and vcc voltage levels region 1: i/o buffers are off region 2: i/o buffers are on. i/os are functional but slower because vcci / vcc are below specification. for the same reason, input buffers do not meet vih/vil levels, and output buffers to not meet voh / vol levels. min vcci datasheet specification voltage at a selected i/o standard; i.e., 1.425 v or 1.7 v or 2.3 v or 3.0 v vcc vcc = 1.425 v region 1: i/o buffers are off activation trip point: v a = 0.85 v 0.25 v d eactivation trip point: v d = 0.75 v 0.25 v activation trip point: v a = 0.9 v 0.3 v deactivation trip point: v d = 0.8 v 0.3 v vcc = 1.575 v region 5: i/o buffers are on and power supplies are within specification. i/os meet the entire datasheet and timer specifications for speed, vih / vil , voh / vol , etc. region 4: i/o buffers are on. i/os are functional but slower because vcci is below specification. for the same reason, input buffers do not meet vih / vil levels, and output buffers do not meet voh/vol levels. where vt can be from 0.58 v to 0.9 v (typically 0.75 v) v cci region 3: i/o buffers are on. i/os are functional; i/o dc specifications are met, but i/os are slower because the vcc is below specification. vcc = vcci + vt
igloo nano low power flash fpgas revision 17 2-5 figure 2-2 ? v2 devices ? i/o state as a function of vcci and vcc voltage levels region 1: i/o buffers are off region 2: i/o buffers are on. i/os are functional but slower because vcci / vcc are below specification. for the same reason, input buffers do not meet vih / vil levels, and output buffers do not meet voh/vol levels. min vcci datasheet specification voltage at a selected i/o standard; i.e., 1.14 v,1.425 v, 1.7 v, 2.3 v, or 3.0 v vcc vcc = 1.14 v region 1: i/o buffers are off activation trip point: v a = 0.85 v 0.2 v d eactivation trip point: v d = 0.75 v 0.2 v activation trip point: v a = 0.9 v 0.15 v deactivation trip point: v d = 0.8 v 0.15 v v cc = 1.575 v region 5: i/o buffers are on and power supplies are within specification. i/os meet the entire datasheet and timer specifications for speed, vih / vil , voh / vol , etc. region 4: i/o buffers are on. i/os are functional but slower because v cci is below specification. for the same reason, input buffers do not meet vih / vil levels, and output buffers do not meet voh / vol levels. where vt can be from 0.58 v to 0.9 v (typically 0.75 v) vcci region 3: i/o buffers are on. i/os are functional; i/o dc specifications are met, but i/os are slower because the vcc is below specification. vcc = vcci + vt
igloo nano dc and switching characteristics 2-6 revision 17 thermal characteristics introduction the temperature variable in the micr osemi designer software refers to the junction temperature, not the ambient temperature. this is an important distin ction because dynamic and static power consumption cause the chip junction temperature to be higher than the ambient temperature. eq 1 can be used to calculate junction temperature. t j = junction temperature = ? t + t a eq 1 where: t a = ambient temperature ? t = temperature gradient between junction (silicon) and ambient ? t = ? ja * p ? ja = junction-to-ambient of the package. ? ja numbers are located in figure 2-5 . p = power dissipation package thermal characteristics the device junction-to-case thermal resistivity is ? jc and the junction-to-ambient air thermal resistivity is ? ja . the thermal characteristics for ? ja are shown for two air flow rates. the maximum operating junction temperature is 100c. eq 2 shows a sample calculation of th e maximum operating power dissipation allowed for a 484-pin fbga package at commercial temperature and in still air. eq 2 temperature and volt age derating factors maximum power allowed max. junction temp. ( ? c) max. ambient temp. ( ? c) ? ? ja ( ? c/w) ------------------------------------------------------------------------------------------------------------------------------- ----------- 100 ? c70 ? c ? 20.5c/w ------------------------------------- 1.46 w = = = table 2-5 ? package thermal resistivities package type pin count ? jc ? ja units still air 200 ft./ min. 500 ft./ min. chip scale package (csp) 36 tbd tbd tbd tbd c/w 81 tbd tbd tbd tbd c/w quad flat no lead (qfn) 48 tbd tbd tbd tbd c/w 68 tbd tbd tbd tbd c/w 100 tbd tbd tbd tbd c/w very thin quad flat pack (vqfp) 100 10.0 35.3 29.4 27.1 c/w table 2-6 ? temperature and voltage derating factor s for timing delays (normalized to t j = 70c, vcc = 1.425 v) for igloo nano v2 or v5 devices, 1.5 v dc core supply voltage array voltage vcc (v) junction temperature (c) ?40c ?20c 0c 25c 70c 85c 100c 1.425 0.947 0.956 0.965 0. 978 1.000 1.009 1.013 1.5 0.875 0.883 0.892 0. 904 0.925 0.932 0.937 1.575 0.821 0.829 0.837 0. 848 0.868 0.875 0.879
igloo nano low power flash fpgas revision 17 2-7 calculating power dissipation quiescent supply current quiescent supply current (idd) calculation depends on multiple factors, including operating voltages (vcc, vcci, and vjtag), operati ng temperature, system clock frequency, and power mode usage. microsemi recommends using the power calculator and smartpower software estimation tools to evaluate the projected static and active power bas ed on the user design, pow er mode usage, operating voltage, and temperature. table 2-7 ? temperature and voltage derating factor s for timing delays (normalized to t j = 70c, vcc = 1.14 v) for igloo nano v2, 1.2 v dc core supply voltage array voltage vcc (v) junction temperature (c) ?40c ?20c 0c 25c 70c 85c 100c 1.14 0.968 0.974 0.979 0.991 1.000 1.006 1.009 1.2 0.863 0.868 0.873 0.884 0.892 0.898 0.901 1.26 0.792 0.797 0.801 0.811 0.819 0.824 0.827 table 2-8 ? power supply state per mode modes/power supplies power supply configurations vcc vccpll vcci vjtag vpump flash*freeze on on on on on/off/floating sleep off off on off off shutdown off off off off off no flash*freeze on on on on on/off/floating note: off: power supply level = 0 v table 2-9 ? quiescent supply current (idd) characte ristics, igloo nano flash*freeze mode* core voltage agln010 agln015 agln020 agln060 agln125 agln250 units typical (25c) 1.2 v 1.9 3.3 3.3 8 13 20 a 1.5 v 5.8 6 6 10 18 34 a note: *idd includes vcc, vpump, vcci, vccpll, and vmv curr ents. values do not include i/o static contribution, which is shown in table 2-13 on page 2-9 through table 2-14 on page 2-9 and table 2-15 on page 2-10 through table 2-18 on page 2-11 (pdc6 and pdc7).
igloo nano dc and switching characteristics 2-8 revision 17 table 2-10 ? quiescent supply current (idd) charac teristics, igloo nano sleep mode* core voltage agln010 agln015 agln020 agln060 agln125 agln250 units vcci= 1.2 v (per bank) typical (25c) 1.2 v 1.7 1.7 1.7 1.7 1.7 1.7 a vcci = 1.5 v (per bank) typical (25c) 1.2 v / 1.5 v 1.8 1.8 1.8 1.8 1.8 1.8 a vcci = 1.8 v (per bank) typical (25c) 1.2 v / 1.5 v 1.9 1.9 1.9 1.9 1.9 1.9 a vcci = 2.5 v (per bank) typical (25c) 1.2 v / 1.5 v 2.2 2.2 2.2 2.2 2.2 2.2 a vcci = 3.3 v (per bank) typical (25c) 1.2 v / 1.5 v 2.5 2.5 2.5 2.5 2.5 2.5 a note: *i dd = n banks * i cci . table 2-11 ? quiescent supply current (idd) characte ristics, igloo nano shutdown mode core voltage agln010 agln015 agl n020 agln060 agln125 agln250 units typical (25c) 1.2 v / 1.5 v 0 0 0 0 0 0 a table 2-12 ? quiescent supply current (idd), no igloo nano flash*freeze mode 1 core voltage agln010 agln015 agln020 agln060 agln125 agln250 units icca current 2 typical (25c) 1.2 v 3.7 5 5 10 13 18 a 1.5 v 8 14 14 20 28 44 a icci or ijtag current vcci / vjtag = 1.2 v (per bank) typical (25c) 1.2 v 1.7 1.7 1.7 1.7 1.7 1.7 a vcci / vjtag = 1.5 v (per bank) typical (25c) 1.2 v / 1.5 v 1.8 1.8 1.8 1.8 1.8 1.8 a vcci / vjtag = 1.8 v (per bank) typical (25c) 1.2 v / 1.5 v 1.9 1.9 1.9 1.9 1.9 1.9 a vcci / vjtag = 2.5 v (per bank) typical (25c) 1.2 v / 1.5 v 2.2 2.2 2.2 2.2 2.2 2.2 a vcci / vjtag = 3.3 v (per bank) typical (25c) 1.2 v / 1.5 v 2.5 2.5 2.5 2.5 2.5 2.5 a notes: 1. idd = n banks * icci + icca. jtag counts as one bank when powered. 2. includes vcc, vccpll, and vpump currents.
igloo nano low power flash fpgas revision 17 2-9 power per i/o pin table 2-13 ? summary of i/o input buffe r power (per pin) ? defa ult i/o software settings applicable to igloo nano i/o banks vcci (v) dynamic power pac9 (w/mhz) 1 single-ended 3.3 v lvttl / 3.3 v lvcmos 3.3 16.38 3.3 v lvttl / 3.3 v lvcmos ? schmitt trigger 3.3 18.89 3.3 v lvcmos wide range 2 3.3 16.38 3.3 v lvcmos wide range ? schmitt trigger 3.3 18.89 2.5 v lvcmos 2.5 4.71 2.5 v lvcmos ? schmitt trigger 2.5 6.13 1.8 v lvcmos 1.8 1.64 1.8 v lvcmos ? schmitt trigger 1.8 1.79 1.5 v lvcmos (jesd8-11) 1.5 0.97 1.5 v lvcmos (jesd8-11) ? schmitt trigger 1.5 0.96 1.2 v lvcmos 3 1.2 0.57 1.2 v lvcmos ? schmitt trigger 3 1.2 0.52 1.2 v lvcmos wide range 3 1.2 0.57 1.2 v lvcmos wide range ? schmitt trigger 3 1.2 0.52 notes: 1. pac9 is the total dynamic power measured on v cci . 2. all lvcmos 3.3 v software macros support lvcmos 3.3 v wide range as specified in the jesd8-b specification. 3. applicable to igloo nano v2 devices operating at vcci ? vcc. table 2-14 ? summary of i/o output bu ffer power (per pin) ? de fault i/o softw are settings 1 applicable to igloo nano i/o banks c load (pf) vcci (v) dynamic power pac10 (w/mhz) 2 single-ended 3.3 v lvttl / 3.3 v lvcmos 5 3.3 107.98 3.3 v lvcmos wide range 3 5 3.3 107.98 2.5 v lvcmos 5 2.5 61.24 1.8 v lvcmos 5 1.8 31.28 1.5 v lvcmos (jesd8-11) 5 1.5 21.50 1.2 v lvcmos 4 51.2 15.22 notes: 1. dynamic power consumption is given for standard load and software default drive strength and output slew. 2. pac10 is the total dynamic power measured on vcci. 3. all lvcmos 3.3 v software macros support lvcmos 3.3 v wide range as specified in the jesd8-b specification. 4. applicable for igloo nano v2 devices operating at vcci ? vcc.
igloo nano dc and switching characteristics 2-10 revision 17 power consumption of vari ous internal resources table 2-15 ? different components contributing to dynamic power consumption in igloo nano devices for igloo nano v2 or v5 devic es, 1.5 v core supply voltage parameter definition device specific dynamic power (w/mhz) agln250 agln125 agln060 agln020 agln015 agln010 pac1 clock contribution of a global rib 4.421 4.493 2.700 0 0 0 pac2 clock contribution of a global spine 2.704 1.976 1.982 4.002 4.002 2.633 pac3 clock contribution of a versat ile row 1.496 1.504 1.511 1.346 1.346 1.340 pac4 clock contribution of a versatile used as a sequential module 0.152 0.153 0.153 0.148 0.148 0.143 pac5 first contribution of a versatile used as a sequential module 0.057 pac6 second contribution of a versatile used as a sequential module 0.207 pac7 contribution of a versatile used as a combinatorial module 0.17 pac8 average contribution of a routing net 0.7 pac9 contribution of an i/o input pin (standard-dependent) see table 2-13 on page 2-9 . pac10 contribution of an i/o output pin (standard-dependent) see ta b l e 2 - 1 4 . pac11 average contribution of a ram block during a read operation 25.00 n/a pac12 average contribution of a ram block during a write operation 30.00 n/a pac13 dynamic contribution for pll 2.70 n/a table 2-16 ? different components contributing to the static power consumption in igloo nano devices for igloo nano v2 or v5 devic es, 1.5 v core supply voltage parameter definition device -specific static power (mw) agln250 agln125 agln060 agln020 agln015 agln010 pdc1 array static powe r in active mode see table 2-12 on page 2-8 pdc2 array static power in static (idle) mode see table 2-12 on page 2-8 pdc3 array static power in flash*freeze mode see table 2-9 on page 2-7 pdc4 1 static pll contribution 1.84 n/a pdc5 bank quiescent power (vcci-dependent) 2 see table 2-12 on page 2-8 notes: 1. minimum contribution of the pll when running at lowest frequency. 2. for a different output load, drive strength, or slew ra te, microsemi recommends using the microsemi power spreadsheet calculator or the smartpower tool in libero soc.
igloo nano low power flash fpgas revision 17 2-11 table 2-17 ? different components contributing to dynamic power consumption in igloo nano devices for igloo nano v2 devices, 1.2 v core supply voltage parameter definition device-specific dynamic power (w/mhz) agln250 agln125 agln060 agln020 agln015 agln010 pac1 clock contribution of a global rib 2.829 2.875 1.728 0 0 0 pac2 clock contribution of a global spine 1.731 1.265 1.268 2.562 2.562 1.685 pac3 clock contribution of a versatile row 0.957 0.963 0.967 0.862 0.862 0.858 pac4 clock contribution of a versatile used as a sequential module 0.098 0.098 0.098 0.094 0.094 0.091 pac5 first contribution of a versatile used as a sequential module 0.045 pac6 second contribution of a versatile used as a sequential module 0.186 pac7 contribution of a versatile used as a combinatorial module 0.11 pac8 average contributio n of a routing net 0.45 pac9 contribution of an i/o input pin (standard-dependent) see table 2-13 on page 2-9 pac10 contribution of an i/o output pin (standard-dependent) see table 2-14 on page 2-9 pac11 average contribution of a ram block during a read operation 25.00 n/a pac12 average contribution of a ram block during a write operation 30.00 n/a pac13 dynamic contribution for pll 2.10 n/a table 2-18 ? different components contributing to the static power consumption in igloo nano devices for igloo nano v2 devices, 1.2 v core supply voltage parameter definition device-specific static power (mw) agln250 agln125 agln060 agln020 agln015 agln010 pdc1 array static power in active mode see table 2-12 on page 2-8 pdc2 array static power in static (idle) mode see table 2-12 on page 2-8 pdc3 array static power in flash*freeze mode see table 2-9 on page 2-7 pdc4 1 static pll contribution 0.90 n/a pdc5 bank quiescent power (vcci-dependent) 2 see table 2-12 on page 2-8 notes: 1. minimum contribution of the pll when running at lowest frequency. 2. for a different output load, drive strength, or slew ra te, microsemi recommends using the microsemi power spreadsheet calculator or the smartpower tool in libero soc.
igloo nano dc and switching characteristics 2-12 revision 17 power calculation methodology this section describes a simplified method to estima te power consumption of an application. for more accurate and detailed power estimations, use t he smartpower tool in libero soc software. the power calculation methodology described below uses the following variables: ? the number of plls as well as the number a nd the frequency of each output clock generated ? the number of combinatorial and sequential cells used in the design ? the internal clock frequencies ? the number and the standard of i/o pins used in the design ? the number of ram blocks used in the design ? toggle rates of i/o pins as well as versatiles?guidelines are provided in table 2-19 on page 2-14 . ? enable rates of output buffers?guidelines are provided for typical applications in table 2-20 on page 2-14 . ? read rate and write rate to the memory?guidel ines are provided for typical applications in table 2-20 on page 2-14 . the calculation should be repeated for each clock domain defined in the design. methodology total power consumption?p total p total = p stat + p dyn p stat is the total static power consumption. p dyn is the total dynamic power consumption. total static power consumption?p stat p stat = (pdc1 or pdc2 or pdc3) + n banks * pdc5 n banks is the number of i/o banks powered in the design. total dynamic power consumption?p dyn p dyn = p clock + p s-cell + p c-cell + p net + p inputs + p outputs + p memory + p pll global clock contribution?p clock p clock = (pac1 + n spine * pac2 + n row * pac3 + n s-cell * pac4) * f clk n spine is the number of global spines us ed in the user design?guidelines are provided in the "spine architecture" section of the igloo nano fpga fabric user's guide . n row is the number of versatile rows used in the design?guidelines are provided in the "spine architecture" section of the igloo nano fpga fabric user's guide . f clk is the global clock signal frequency. n s-cell is the number of versatiles used as sequential modules in the design. pac1, pac2, pac3, and pac4 are device-dependent. sequential cells contribution?p s-cell p s-cell = n s-cell * (pac5 + ? 1 / 2 * pac6) * f clk n s-cell is the number of versatiles used as sequential modules in the design. when a multi-tile sequential cell is used, it should be accounted for as 1. ? 1 is the toggle rate of versatile outputs?guidelines are provided in table 2-19 on page 2-14 . f clk is the global clock signal frequency.
igloo nano low power flash fpgas revision 17 2-13 combinatorial cells contribution?p c-cell p c-cell = n c-cell * ? 1 / 2 * pac7 * f clk n c-cell is the number of versatiles used as combinatorial modules in the design. ? 1 is the toggle rate of versatile outputs?guidelines are provided in table 2-19 on page 2-14 . f clk is the global clock signal frequency. routing net contribution?p net p net = (n s-cell + n c-cell ) * ? 1 / 2 * pac8 * f clk n s-cell is the number of versatiles used as sequential modules in the design. n c-cell is the number of versatiles used as combinatorial modules in the design. ? 1 is the toggle rate of versatile outputs?guidelines are provided in table 2-19 on page 2-14 . f clk is the global clock signal frequency. i/o input buffer contribution?p inputs p inputs = n inputs * ? 2 / 2 * pac9 * f clk n inputs is the number of i/o input buffers used in the design. ? 2 is the i/o buffer toggle rate?guidelines are provided in table 2-19 on page 2-14 . f clk is the global clock signal frequency. i/o output buffer contribution?p outputs p outputs = n outputs * ? 2 / 2 * ? 1 * pac10 * f clk n outputs is the number of i/o output buffers used in the design. ? 2 is the i/o buffer toggle rate?guidelines are provided in table 2-19 on page 2-14 . ? 1 is the i/o buffer enable rate?guidelines are provided in table 2-20 on page 2-14 . f clk is the global clock signal frequency. ram contribution?p memory p memory = pac11 * n blocks * f read-clock * ? 2 + pac12 * n block * f write-clock * ? 3 n blocks is the number of ram blocks used in the design. f read-clock is the memory read clock frequency. ? 2 is the ram enable rate for read operations. f write-clock is the memory write clock frequency. ? 3 is the ram enable rate for write operations?guidelines are provided in table 2-20 on page 2-14 . pll contribution?p pll p pll = pdc4 + pac13 *f clkout f clkout is the output clock frequency. 1 1. if a pll is used to generate more than one output clock, incl ude each output clock in the formula by adding its corresponding contribution (pac13* fclkout product) to the total pll contribution.
igloo nano dc and switching characteristics 2-14 revision 17 guidelines toggle rate definition a toggle rate defines the frequency of a net or logic elem ent relative to a clock. it is a percentage. if the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. below are some examples: ? the average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency. ? the average toggle rate of an 8-bit counter is 25%: ? bit 0 (lsb) = 100% ? bit 1 = 50% ? bit 2 = 25% ?? ? bit 7 (msb) = 0.78125% ? average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 enable rate definition output enable rate is the average percentage of ti me during which tristate outputs are enabled. when nontristate output buffers are used, the enable rate should be 100%. table 2-19 ? toggle rate guidelines recommended for power calculation component definition guideline ? 1 toggle rate of versatile outputs 10% ? 2 i/o buffer toggle rate 10% table 2-20 ? enable rate guidelines reco mmended for power calculation component definition guideline ? 1 i/o output buffer enable rate 100% ? 2 ram enable rate for read operations 12.5% ? 3 ram enable rate for write operations 12.5%
igloo nano low power flash fpgas revision 17 2-15 user i/o characteristics timing model figure 2-3 ? timing model operating conditions: std speed, commercial temperature range (t j = 70c), worst-case vcc = 1.425 v, for dc 1.5 v core voltag e, applicable to v2 and v5 devices dq y y dq dq dq y combinational cell combinational cell combinational cell i/o module (registered) i/o module (non-registered) register cell register cell i/o module (registered) i/o module (non-registered) lvcmos 2.5 v output drive strength = 8 ma high slew rate input lvcmos 2.5 v lvcmos 1.5 v lvttl 3.3 v output drive strength = 8 ma high slew rate y combinational cell y combinational cell y combinational cell i/o module (non-registered) lvttl output drive strength = 8 ma high slew rate i/o module (non-registered) lvcmos 1.5 v output drive strength = 2 ma high slew rate lvttl output drive strength = 4 ma high slew rate i/o module (non-registered) input lvttl clock input lvttl clock input lvttl clock t pd = 1.18 ns t pd = 0.90 ns t dp = 1.99 ns t pd = 1.60 ns t dp = 2.35 ns t pd = 1.17 ns t dp = 1.96 ns t pd = 0.87 ns t dp = 2.65 ns t pd = 0.91 ns t py = 0.85 ns t clkq = 0.89 ns t oclkq = 1.00 ns t sud = 0.81 ns t osud = 0.51 ns t dp = 1.96 ns t py = 0.85 ns t py = 1.15 ns t clkq = 0.89 ns t sud = 0.81 ns t py = 0.85 ns t iclkq = 0.42 ns t isud = 0.47 ns t py = 1.06 ns
igloo nano dc and switching characteristics 2-16 revision 17 figure 2-4 ? input buffer timing model and delays (example) t py (r) pad y v trip gnd t py (f) v trip 50% 50% vih vcc vil t din (r) din gnd t din (f) 50% 50% vcc pad y t py d clk q i/o interface din t din to array t py = max(t py (r), t py (f)) t din = max(t din (r), t din (f))
igloo nano low power flash fpgas revision 17 2-17 figure 2-5 ? output buffer model and delays (example) t dp (r) pad v ol t dp (f) vtrip vtrip voh vcc d 50% 50% vcc 0 v dout 50% 50% 0 v t dout (r) t dout (f) from array pad t dp std load d clk q i/o interface dout d t dout t dp = max(t dp (r), t dp (f)) t dout = max(t dout (r), t dout (f))
igloo nano dc and switching characteristics 2-18 revision 17 figure 2-6 ? tristate output buffer timing model and delays (example) d clk q d clk q 10% v cci t zl vtrip 50% t hz 90% vcci t zh vtrip 50% 50% t lz 50% eout pad d e 50% t eout (r) 50% t eout (f) pad dout eout d i/o interface e t eout t zls vtrip 50% t zhs vtrip 50% eout pad d e 50% 50% t eout (r) t eout (f) 50% vcc vcc vcc vcci vcc vcc vcc voh vol vol t zl , t zh , t hz , t lz , t zls , t zhs t eout = max(t eout (r), t eout (f))
igloo nano low power flash fpgas revision 17 2-19 overview of i/o performance summary of i/o dc input and output levels ? default i/o software settings table 2-21 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions?softwar e default settings i/o standard drive strength equivalent software default drive strength 2 slew rate vil vih vol voh iol 1 ioh 1 min. v max. v min. v max. v max. v min. vmama 3.3 v lvttl / 3.3 v lvcmos 8 ma 8 ma high ?0.3 0.8 2 3.6 0.4 2.4 8 8 3.3 v lvcmos wide range 3 100 a 8 ma high ?0.3 0.8 2 3.6 0.2 vcci ? 0.2 100 a 100 a 2.5 v lvcmos 8 ma 8 ma high ?0.3 0.7 1.7 3.6 0.7 1.7 8 8 1.8 v lvcmos 4 ma 4 ma high ?0.3 0.35 * v cci 0.65 * vcci 3.6 0.45 vcci ? 0.45 4 4 1.5 v lvcmos 2 ma 2 ma high ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.25 * vcci 0.75 * vcci 2 2 1.2 v lvcmos 4 1 ma 1 ma high ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.25 * vcci 0.75 * vcci 1 1 1.2 v lvcmos wide range 4,5 100 a 1 ma high ?0.3 0.3 * vcci 0.7 * vcci 3.6 0.1 vcci ? 0.1 100 a 100 a notes: 1. currents are measured at 85c junction temperature. 2. the minimum drive strength for any lvcmos 1.2 v or lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 3. all lvcmos 3.3 v software macros support lvcmos 3.3 v wide range, as specified in the jesd8-b specification. 4. applicable to igloo nano v2 devices operating at vcci ?? vcc . 5. all lvcmos 1.2 v software macros support lvcmos 1.2 v wide range, as specified in the jesd8-12 specification. table 2-22 ? summary of maximum and minimum dc input levels applicable to commercial and industrial conditions dc i/o standards commercial 1 industrial 2 iil 3 iih 4 iil 3 iih 4 a a a a 3.3 v lvttl / 3.3 v lvcmos 10 10 15 15 3.3 v lvcoms wide range 10 10 15 15 2.5 v lvcmos 10 10 15 15 1.8 v lvcmos 10 10 15 15 1.5 v lvcmos 10 10 15 15 1.2 v lvcmos 5 10 10 15 15 1.2 v lvcmos wide range 5 10 10 15 15 notes: 1. commercial range (?20c < t a < 70c) 2. industrial range (?40c < t a < 85c) 3. i ih is the input leakage current per i/o pin over recommended operating conditions, where vih < vin < vcci. input current is larger when operating outside recommended ranges. 4. i il is the input leakage current per i/o pin over re commended operating conditions, where ?0.3 v < vin < vil. 5. applicable to igloo nano v2 devices operating at vcci ?? vcc.
igloo nano dc and switching characteristics 2-20 revision 17 summary of i/o timing characteristi cs ? default i/o software settings table 2-23 ? summary of ac measuring points standard measuring trip point (vtrip) 3.3 v lvttl / 3.3 v lvcmos 1.4 v 3.3 v lvcmos wide range 1.4 v 2.5 v lvcmos 1.2 v 1.8 v lvcmos 0.90 v 1.5 v lvcmos 0.75 v 1.2 v lvcmos 0.60 v 1.2 v lvcmos wide range 0.60 v table 2-24 ? i/o ac parameter definitions parameter parameter definition t dp data to pad delay through the output buffer t py pad to data delay through the input buffer t dout data to output buffer delay through the i/o interface t eout enable to output buffer tristate control delay through the i/o interface t din input buffer to data delay through the i/o interface t hz enable to pad delay through the output buffer?high to z t zh enable to pad delay through the output buffer?z to high t lz enable to pad delay through the output buffer?low to z t zl enable to pad delay through the output buffer?z to low t zhs enable to pad delay through the output buffer with delayed enable?z to high t zls enable to pad delay through the output buffer with delayed enable?z to low
igloo nano low power flash fpgas revision 17 2-21 applies to igloo nano at 1.5 v core operating conditions table 2-25 ? summary of i/o timing character istics?software default settings std speed grade, commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v i/o standard drive strength (ma) equivalent software default t drive strength option 1 slew rate capacitive load (pf) t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 3.3 v lvttl / 3.3 v lvcmos 8 ma 8 ma high 5 pf 0.97 1.79 0.19 0.86 1.16 0.66 1.83 1.45 1.98 2.38 ns 3.3 v lvcmos wide range 2 100 a 8 ma high 5 pf 0.97 2.56 0.19 1. 20 1.66 0.66 2.57 2.02 2.82 3.31 ns 2.5 v lvcmos 8 ma 8 ma high 5 pf 0.97 1. 81 0.19 1.10 1.24 0.66 1.85 1.63 1.97 2.26 ns 1.8 v lvcmos 4 ma 4 ma high 5 pf 0.97 2. 08 0.19 1.03 1.44 0.66 2.12 1.95 1.99 2.19 ns 1.5 v lvcmos 2 ma 2 ma high 5 pf 0.97 2. 39 0.19 1.19 1.52 0.66 2.44 2.24 2.02 2.15 ns notes: 1. the minimum drive strength for any lvcmos 1.2 v or lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. all lvcmos 3.3 v software macros support lvcmos 3.3 v wide range, as specified in the jesd8-b specification. 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo nano dc and switching characteristics 2-22 revision 17 applies to igloo nano at 1.2 v core operating conditions table 2-26 ? summary of i/o timing character istics?software default settings std speed grade, commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 3.0 v i/o standard drive strength (ma) equiv. software default drive strength option 1 slew rate capacitive load (pf) t dout t dp t din t py ) t pys t eout t zl t zh t lz t hz units 3.3 v lvttl / 3.3 v lvcmos 8 ma 8 ma high 5 pf 1.55 2.31 0.26 0. 97 1.36 1.10 2.34 1.90 2.43 3.14 ns 3.3 v lvcmos wide range 2 100 a 8 ma high 5 pf 1.55 3.25 0.26 1. 31 1.91 1.10 3.25 2.61 3.38 4.27 ns 2.5 v lvcmos 8 ma 8 ma high 5 pf 1.55 2.30 0.26 1.21 1.39 1.10 2. 33 2.04 2.41 2.99 ns 1.8 v lvcmos 4 ma 4 ma high 5 pf 1.55 2.49 0.26 1.13 1.59 1.10 2. 53 2.34 2.42 2.81 ns 1.5 v lvcmos 2 ma 2 ma high 5 pf 1.55 2.78 0.26 1.27 1.77 1.10 2. 82 2.62 2.44 2.74 ns 1.2 v lvcmos 1 ma 1 ma high 5 pf 1.55 3.50 0.26 1.56 2.27 1.10 3. 37 3.10 2.55 2.66 ns 1.2 v lvcmos wide range 3 100 a 1 ma high 5 pf 1.55 3.50 0.26 1. 56 2.27 1.10 3.37 3.10 2.55 2.66 ns notes: 1. the minimum drive strength for any lvcmos 1.2 v or lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models.. 2. all lvcmos 3.3 v software macros support lvcmos 3.3 v wide range, as specified in the jesd8-b specification. 3. all lvcmos 1.2 v software macros support lvcmos 1.2 v side range as specified in the jesd8-12 specification. 4. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo nano low power flash fpgas revision 17 2-23 detailed i/o dc characteristics table 2-27 ? input capacitance symbol definition conditions min. max. units c in input capacitance vin = 0, f = 1.0 mhz 8 pf c inclk input capacitance on the clock pin vin = 0, f = 1.0 mhz 8 pf table 2-28 ? i/o output buffer maximum resistances 1 standard drive strength r pull-down ( ? ) 2 r pull-up ( ? ) 3 3.3 v lvttl / 3.3v lvcmos 2 ma 100 300 4 ma 100 300 6 ma 50 150 8 ma 50 150 3.3 v lvcmos wide range 100 a same as equivalent software default drive 2.5 v lvcmos 2 ma 100 200 4 ma 100 200 6 ma 50 100 8 ma 50 100 1.8 v lvcmos 2 ma 200 225 4 ma 100 112 1.5 v lvcmos 2 ma 200 224 1.2 v lvcmos 4 1 ma 315 315 1.2 v lvcmos wide range 4 100 a 315 315 notes: 1. these maximum values are provided for informational reasons only. minimum output buffer resistance values depend on vcci, drive strength selection, temperature, and process. for board design considerations and detailed output buffer resistances, use the corresponding ibis models posted at http://www.microsem i.com/soc/dow nload/ibis/de fault.aspx . 2. r (pull-down-max) = (volspec) / iolspec 3. r (pull-up-max) = (vccimax ? vohspec) / i ohspec 4. applicable to igloo nano v2 devices operating at vcci ? vcc.
igloo nano dc and switching characteristics 2-24 revision 17 table 2-29 ? i/o weak pull-up/pull-down resistances minimum and maximum weak pull-u p/pull-down resistance values vcci r (weak pull-up) 1 ( ? )r (weak pull-down) 2 ( ? ) min. max. min. max. 3.3 v 10 k 45 k 10 k 45 k 3.3 v (wide range i/os) 10 k 45 k 10 k 45 k 2.5 v 11 k 55 k 12 k 74 k 1.8 v 18 k 70 k 17 k 110 k 1.5 v 19 k 90 k 19 k 140 k 1.2 v 25 k 110 k 25 k 150 k 1.2 v (wide range i/os) 19 k 110 k 19 k 150 k notes: 1. r (weak pull-up-max) = (v ccimax ? vohspec) / i (weak pull-up-min ) 2. r (weak pull-down-max) = (volspec) / i (weak pull-down-min) table 2-30 ? i/o short currents iosh/iosl drive strength iosl (ma)* iosh (ma)* 3.3 v lvttl / 3.3 v lvcmos 2 ma 25 27 4 ma 25 27 6 ma 51 54 8 ma 51 54 3.3 v lvcmos wide range 100 a same as equivalent software default drive 2.5 v lvcmos 2 ma 16 18 4 ma 16 18 6 ma 32 37 8 ma 32 37 1.8 v lvcmos 2 ma 9 11 4 ma 17 22 1.5 v lvcmos 2 ma 13 16 1.2 v lvcmos 1 ma 10 13 1.2 v lvcmos wide range 100 a 10 13 note: *t j = 100c
igloo nano low power flash fpgas revision 17 2-25 the length of time an i/o can withstand iosh/iosl events depends on the junc tion temperature. the reliability data below is based on a 3.3 v, 8 ma i/o setting, which is the worst case for this type of analysis. for example, at 100c, the short current condition would have to be sustained for more than six months to cause a reliability concern. the i/o design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. table 2-31 ? duration of short circui t event before failure temperature time before failure ?40c > 20 years ?20c > 20 years 0c > 20 years 25c > 20 years 70c 5 years 85c 2 years 100c 6 months table 2-32 ? schmitt trigger input hysteresis hysteresis voltage value (typ.) for schmitt mode input buffers input buffer conf iguration hysteresis value (typ.) 3.3 v lvttl / lvcmos (schmitt trigger mode) 240 mv 2.5 v lvcmos (schmitt trigger mode) 140 mv 1.8 v lvcmos (schmitt trigger mode) 80 mv 1.5 v lvcmos (schmitt trigger mode) 60 mv 1.2 v lvcmos (schmitt trigger mode) 40 mv table 2-33 ? i/o input rise time, fall time , and related i/o reliability input buffer input rise/fall time (min.) input rise/fall time (max.) reliability lvttl/lvcmos (schmitt trigger disabled) no requirement 10 ns * 20 years (100c) lvttl/lvcmos (schmitt trigger enabled) no requirement no requirement, but input noise voltage cannot exceed schmitt hysteresis. 20 years (100c) note: *the maximum input rise/fall time is related to t he noise induced into the input buffer trace. if the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. the longer the rise/fall times, the more susceptible the input signal is to the board noise. microsemi recommends signal integrity eval uation/characterization of the system to ensure that there is no excessive noise coupling into input signals.
igloo nano dc and switching characteristics 2-26 revision 17 single-ended i/o characteristics 3.3 v lvttl / 3.3 v lvcmos low-voltage transistor?transistor logic (lvttl) is a general purpose standard (eia/jesd) for 3.3 v applications. it uses an lvttl input buffer and push-pull output buffer. table 2-34 ? minimum and maximum dc input and output levels 3.3 v lvttl / 3.3 v lvcmos vil vih vol voh iol ioh iosl iosh iil 1 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 2 ma ?0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10 4 ma ?0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10 6 ma ?0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10 8 ma ?0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10 notes: 1. i il is the input leakage current per i/o pin over recommended operating conditions where ?0.3 < vin < vil. 2. i ih is the input leakage current per i/o pin over recommended operating conditions where vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. software default selection highlighted in gray. figure 2-7 ? ac loading table 2-35 ? 3.3 v lvttl/lvcmos ac waveforms, m easuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 03.31.45 note: *measuring point = vtrip. see table 2-23 on page 2-20 for a complete table of trip points. test point test point enable path datapath 5 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 5 pf for t zh / t zhs / t zl / t zls 5 pf for t hz / t lz
igloo nano low power flash fpgas revision 17 2-27 timing characteristics applies to 1.5 v dc core voltage table 2-36 ? 3.3 v lvttl / 3.3 v lvcmos low slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.97 3.52 0.19 0.86 1.16 0.66 3.59 3.42 1.75 1.90 ns 4 ma std 0.97 3.52 0.19 0.86 1.16 0.66 3.59 3.42 1.75 1.90 ns 6 ma std 0.97 2.90 0.19 0.86 1.16 0.66 2.96 2.83 1.98 2.29 ns 8 ma std 0.97 2.90 0.19 0.86 1.16 0.66 2.96 2.83 1.98 2.29 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-37 ? 3.3 v lvttl / 3.3 v lvcmos high slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.97 2.16 0.19 0.86 1.16 0.66 2.20 1.80 1.75 1.99 ns 4 ma std 0.97 2.16 0.19 0.86 1.16 0.66 2.20 1.80 1.75 1.99 ns 6 ma std 0.97 1.79 0.19 0.86 1.16 0.66 1.83 1.45 1.98 2.38 ns 8 ma std 0.97 1.79 0.19 0.86 1.16 0.66 1.83 1.45 1.98 2.38 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo nano dc and switching characteristics 2-28 revision 17 applies to 1.2 v dc core voltage table 2-38 ? 3.3 v lvttl / 3.3 v lvcmos low slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 3.0 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 1.55 4.09 0.26 0.97 1.36 1.10 4.16 3.91 2.19 2.64 ns 4 ma std 1.55 4.09 0.26 0.97 1.36 1.10 4.16 3.91 2.19 2.64 ns 6 ma std 1.55 3.45 0.26 0.97 1.36 1.10 3.51 3.32 2.43 3.03 ns 8 ma std 1.55 3.45 0.26 0.97 1.36 1.10 3.51 3.32 2.43 3.03 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-39 ? 3.3 v lvttl / 3.3 v lvcmos high slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 3.0 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 1.55 2.68 0.26 0.97 1.36 1.10 2.72 2.26 2.19 2.74 ns 4 ma std 1.55 2.68 0.26 0.97 1.36 1.10 2.72 2.26 2.19 2.74 ns 6 ma std 1.55 2.31 0.26 0.97 1.36 1.10 2.34 1.90 2.43 3.14 ns 8 ma std 1.55 2.31 0.26 0.97 1.36 1.10 2.34 1.90 2.43 3.14 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo nano low power flash fpgas revision 17 2-29 3.3 v lvcmos wide range table 2-40 ? minimum and maximum dc input and output levels for lvcmos 3.3 v wide range 3.3 v lvcmos wide range 1 equivalent software default drive strength option 4 vil vih vol voh iol i oh iil 2 iih 3 drive strength min. v max. v min. v max. v max. v min. vaaa 5 a 5 100 a 2 ma ?0.3 0.8 2 3.6 0.2 vcci ? 0.2 100 100 10 10 100 a 4 ma ?0.3 0.8 2 3.6 0.2 vcci ? 0.2 100 100 10 10 100 a 6 ma ?0.3 0.8 2 3.6 0.2 vcci ? 0.2 100 100 10 10 100 a 8ma ?0.3 0.8 2 3.6 0.2 vcci ? 0.2 100 100 10 10 notes: 1. all lvcmos 3.3 v software macros support lvcmos 3. 3 v wide range, as specified in the jedec jesd8-b specification. 2. i il is the input leakage current per i/o pin over recommended operating conditions where ?0.3 < vin < vil. 3. i ih is the input leakage current per i/o pin over recommended operating conditions where vih < vin < vcci. input current is larger when operating outside recommended ranges. 4. the minimum drive strength for any lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 5. currents are measured at 85c junction temperature. 6. software default selection is highlighted in gray.
igloo nano dc and switching characteristics 2-30 revision 17 timing characteristics applies to 1.5 v dc core voltage table 2-41 ? 3.3 v lvcmos wide range low slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.7 v drive strength equivalent software default drive strength option 1 speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 100 a 2 ma std 0.97 5.23 0.19 1.20 1.66 0.66 5.24 5.00 2.47 2.56 ns 100 a 4 ma std 0.97 5.23 0.19 1.20 1.66 0.66 5.24 5.00 2.47 2.56 ns 100 a 6 ma std 0.97 4.27 0.19 1.20 1.66 0.66 4.28 4.12 2.83 3.16 ns 100 a 8 ma std 0.97 4.27 0.19 1.20 1.66 0.66 4.28 4.12 2.83 3.16 ns notes: 1. the minimum drive strength for any lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-42 ? 3.3 v lvcmos wide range high slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.7 v drive strength equivalent software default drive strength option 1 speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 100 a 2 ma std 0.97 3.11 0.19 1.20 1.66 0.66 3.13 2.55 2.47 2.70 ns 100 a 4 ma std 0.97 3.11 0.19 1.20 1.66 0.66 3.13 2.55 2.47 2.70 ns 100 a 6 ma std 0.97 2.56 0.19 1.20 1.66 0.66 2.57 2.02 2.82 3.31 ns 100 a 8 ma std 0.97 2.56 0.19 1.20 1.66 0.66 2.57 2.02 2.82 3.31 ns notes: 1. the minimum drive strength for any lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. 3. software default selection highlighted in gray.
igloo nano low power flash fpgas revision 17 2-31 applies to 1.2 v dc core voltage table 2-43 ? 3.3 v lvcmos wide range low slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 2.7 v drive strength equivalent software default drive strength option 1 speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 100 a 2 ma std 1.55 6.01 0.26 1.31 1.91 1.10 6.01 5.66 3.02 3.49 ns 100 a 4 ma std 1.55 6.01 0.26 1.31 1.91 1.10 6.01 5.66 3.02 3.49 ns 100 a 6 ma std 1.55 5.02 0.26 1.31 1.91 1.10 5.02 4.76 3.38 4.10 ns 100 a 8 ma std 1.55 5.02 0.26 1.31 1.91 1.10 5.02 4.76 3.38 4.10 ns notes: 1. the minimum drive strength for any lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-44 ? 3.3 v lvcmos wide range high slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 2.7 v drive strength equivalent software default drive strength option 1 speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 100 a 2 ma std 1.55 3.82 0.26 1.31 1.91 1.10 3.82 3.15 3.01 3.65 ns 100 a 4 ma std 1.55 3.82 0.26 1.31 1.91 1.10 3.82 3.15 3.01 3.65 ns 100 a 6 ma std 1.55 3.25 0.26 1.31 1.91 1.10 3.25 2.61 3.38 4.27 ns 100 a 8 ma std 1.55 3.25 0.26 1.31 1.91 1.10 3.25 2.61 3.38 4.27 ns notes: 1. the minimum drive strength for any lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. 3. software default selection highlighted in gray.
igloo nano dc and switching characteristics 2-32 revision 17 2.5 v lvcmos low-voltage cmos for 2.5 v is an extension of the lvcmos standard (jesd8-5) used for general purpose 2.5 v applications. table 2-45 ? minimum and maximum dc input and output levels 2.5 v lvcmos vil vih vol voh iol ioh iosl iosh iil 1 iih 2 drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 3 max., ma 3 a 4 a 4 2 ma ?0.3 0.7 1.7 3.6 0.7 1.7 2 2 16 18 10 10 4 ma ?0.3 0.7 1.7 3.6 0.7 1.7 4 4 16 18 10 10 6 ma ?0.3 0.7 1.7 3.6 0.7 1.7 6 6 32 37 10 10 8 ma ?0.3 0.7 1.7 3.6 0.7 1.7 8 8 32 37 10 10 notes: 1. i il is the input leakage current per i/o pin over recommended operating conditions where ?0.3 < vin < vil. 2. i ih is the input leakage current per i/o pin over recommended operating conditions where vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. software default selection highlighted in gray. figure 2-8 ? ac loading table 2-46 ? 2.5 v lvcmos ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 02.51.25 note: *measuring point = vtrip. see table 2-23 on page 2-20 for a complete table of trip points. test point test point enable path datapath 5 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 5 pf for t zh / t zhs / t zl / t zls 5 pf for t hz / t lz
igloo nano low power flash fpgas revision 17 2-33 timing characteristics applies to 1.5 v dc core voltage table 2-47 ? 2.5 v lvcmos low slew ? appl ies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.97 4.13 0.19 1.10 1.24 0.66 4.01 4.13 1.73 1.74 ns 4 ma std 0.97 4.13 0.19 1.10 1.24 0.66 4.01 4.13 1.73 1.74 ns 8 ma std 0.97 3.39 0.19 1.10 1.24 0.66 3.31 3.39 1.98 2.19 ns 8 ma std 0.97 3.39 0.19 1.10 1.24 0.66 3.31 3.39 1.98 2.19 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-48 ? 2.5 v lvcmos high slew ? app lies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.97 2.19 0.19 1.10 1.24 0.66 2.23 2.11 1.72 1.80 ns 4 ma std 0.97 2.19 0.19 1.10 1.24 0.66 2.23 2.11 1.72 1.80 ns 6 ma std 0.97 1.81 0.19 1.10 1.24 0.66 1.85 1.63 1.97 2.26 ns 8 ma std 0.97 1.81 0.19 1.10 1.24 0.66 1.85 1.63 1.97 2.26 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo nano dc and switching characteristics 2-34 revision 17 applies to 1.2 v dc core voltage table 2-49 ? 2.5 lvcmos low slew ? appli es to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 2.3 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 1.55 4.61 0.26 1.21 1.39 1.10 4.55 4.61 2.15 2.43 ns 4 ma std 1.55 4.61 0.26 1.21 1.39 1.10 4.55 4.61 2.15 2.43 ns 6 ma std 1.55 3.86 0.26 1.21 1.39 1.10 3.82 3.86 2.41 2.89 ns 8 ma std 1.55 3.86 0.26 1.21 1.39 1.10 3.82 3.86 2.41 2.89 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-50 ? 2.5 v lvcmos high slew ? app lies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 2.3 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 1.55 2.68 0.26 1.21 1.39 1.10 2.72 2.54 2.15 2.51 ns 4 ma std 1.55 2.68 0.26 1.21 1.39 1.10 2.72 2.54 2.15 2.51 ns 6 ma std 1.55 2.30 0.26 1.21 1.39 1.10 2.33 2.04 2.41 2.99 ns 8 ma std 1.55 2.30 0.26 1.21 1.39 1.10 2.33 2.04 2.41 2.99 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo nano low power flash fpgas revision 17 2-35 1.8 v lvcmos low-voltage cmos for 1.8 v is an extension of the lvcmos standard (jesd8-5) used for general purpose 1.8 v applications. it uses a 1.8 v input buffer and a push-pull output buffer. table 2-51 ? minimum and maximum dc input and output levels 1.8 v lvcmos vil vih vol voh iol ioh iosl iosh iil 1 i i h 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 2 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.45 vcci ? 0.45 2 2 9 11 10 10 4 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.45 vcci ? 0.45 4 4 17 22 10 10 notes: 1. i il is the input leakage current per i/o pin over recommended operating conditions where ?0.3 < vin < vil. 2. i ih is the input leakage current per i/o pin over recommended operating conditions where vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. software default selection highlighted in gray. figure 2-9 ? ac loading table 2-52 ? 1.8 v lvcmos ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 01.80.95 note: *measuring point = vtrip. see table 2-23 on page 2-20 for a complete table of trip points. test point test point enable path datapath 5 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 5 pf for t zh / t zhs / t zl / t zls 5 pf for t hz / t lz
igloo nano dc and switching characteristics 2-36 revision 17 timing characteristics applies to 1.5 v dc core voltage applies to 1.2 v dc core voltage table 2-53 ? 1.8 v lvcmos low slew ? appl ies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.7 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.97 5.44 0.19 1.03 1.44 0.66 5.25 5.44 1.69 1.35 ns 4 ma std 0.97 4.44 0.19 1.03 1.44 0.66 4.37 4.44 1.99 2.11 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-54 ? 1.8 v lvcmos high slew ? app lies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.7 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.97 2.64 0.19 1.03 1.44 0.66 2.59 2.64 1.69 1.40 ns 4 ma std 0.97 2.08 0.19 1.03 1.44 0.66 2.12 1.95 1.99 2.19 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-55 ? 1.8 v lvcmos low slew ? appl ies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.7 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 1.55 5.92 0.26 1.13 1.59 1.10 5.72 5.92 2.11 1.95 ns 4 ma std 1.55 4.91 0.26 1.13 1.59 1.10 4.82 4.91 2.42 2.73 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-56 ? 1.8 v lvcmos high slew ? app lies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.7 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 1.55 3.05 0.26 1.13 1.59 1.10 3.01 3.05 2.10 2.00 ns 4 ma std 1.55 2.49 0.26 1.13 1.59 1.10 2.53 2.34 2.42 2.81 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo nano low power flash fpgas revision 17 2-37 1.5 v lvcmos (jesd8-11) low-voltage cmos for 1.5 v is an extension of the lvcmos standard (jesd8-5) used for general purpose 1.5 v applications. it uses a 1.5 v input buffer and a push-pull output buffer. table 2-57 ? minimum and maximum dc input and output levels 1.5 v lvcmos vil vih vol voh iol ioh iosl iosh iil 1 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 2 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.25 * vcci 0.75 * vcci 2 2 13 16 10 10 notes: 1. i il is the input leakage current per i/o pin over recommended operating conditions where ?0.3 < vin < vil. 2. iih is the input leakage current per i/o pin over re commended operating conditions where vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. software default selection highlighted in gray. figure 2-10 ? ac loading table 2-58 ? 1.5 v lvcmos ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 01.50.755 note: *measuring point = vtrip. see table 2-23 on page 2-20 for a complete table of trip points. test point test point enable path datapath 5 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 5 pf for t zh / t zhs / t zl / t zls 5 pf for t hz / t lz
igloo nano dc and switching characteristics 2-38 revision 17 timing characteristics applies to 1.5 v dc core voltage applies to 1.2 v dc core voltage table 2-59 ? 1.5 v lvcmos low slew ? appl ies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.97 5.39 0.19 1.19 1.62 0.66 5.48 5.39 2.02 2.06 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-60 ? 1.5 v lvcmos high slew ? app lies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.97 2.39 0.19 1.19 1.62 0.66 2.44 2.24 2.02 2.15 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-61 ? 1.5 v lvcmos low slew ? appl ies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.4 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 1.55 5.87 0.26 1.27 1.77 1.10 5.92 5.87 2.45 2.65 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-62 ? 1.5 v lvcmos high slew ? app lies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.4 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 1.55 2.78 0.26 1.27 1.77 1.10 2.82 2.62 2.44 2.74 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo nano low power flash fpgas revision 17 2-39 1.2 v lvcmos (jesd8-12a) low-voltage cmos for 1.2 v complies with the lvcm os standard jesd8-12a for general purpose 1.2 v applications. it uses a 1.2 v input buffer and a push-pull output buffer. timing characteristics applies to 1.2 v dc core voltage table 2-63 ? minimum and maximum dc input and output levels 1.2 v lvcmos vil vih vol voh iol ioh iosl iosh iil 1 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 1 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.25 * vcci 0.75 * vcci 1 1 10 13 10 10 notes: 1. i il is the input leakage current per i/o pin over recommended operating conditions where ?0.3 < vin < vil. 2. i ih is the input leakage current per i/o pin over recommended operating conditions where vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. software default selection highlighted in gray. figure 2-11 ? ac loading table 2-64 ? 1.2 v lvcmos ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 01.20.65 note: *measuring point = vtrip. see table 2-23 on page 2-20 for a complete table of trip points. test point test point enable path datapath 5 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 5 pf for t zh / t zhs / t zl / t zls 5 pf for t hz / t lz table 2-65 ? 1.2 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.14 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 1 ma std 1.55 8.30 0.26 1.56 2.27 1.10 7.97 7.54 2.56 2.55 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-66 ? 1.2 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.14 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 1 ma std 1.55 3.50 0.26 1.56 2.27 1.10 3.37 3.10 2.55 2.66 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo nano dc and switching characteristics 2-40 revision 17 1.2 v lvcmos wide range timing characteristics applies to 1.2 v dc core voltage table 2-67 ? minimum and maximum dc input and output levels 1.2 v lvcmos wide range vil vih vol voh iol ioh iosl iosh iil 1 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 1 ma ?0.3 0.3 * vcci 0.7 * vcci 3.6 0.1 vcci ? 0.1 100 100 10 13 10 10 notes: 1. i il is the input leakage current per i/o pin over recommended operating conditions where ?0.3 < vin < vil. 2. i ih is the input leakage current per i/o pin over recommended operating conditions where vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. applicable to igloo nano v2 devices operating at vcci ?? vcc. 6. software default selection highlighted in gray. table 2-68 ? 1.2 v lvcmos wide range low slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.14 v drive strength equivalent software default drive strength option 1 speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 100 a 1 ma std 1.55 8.30 0.26 1.56 2.27 1.10 7.97 7.54 2.56 2.55 ns notes: 1. the minimum drive strength for any lvcmos 1.2 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-69 ? 1.2 v lvcmos wide range high slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 1.14 v drive strength equivalent software default drive strength option 1 speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 100 a 1 ma std 1.55 3.50 0.26 1.56 2.27 1.10 3.37 3.10 2.55 2.66 ns notes: 1. the minimum drive strength for any lvcmos 1.2 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. 3. software default selection highlighted in gray.
igloo nano low power flash fpgas revision 17 2-41 i/o register specifications fully registered i/o buff ers with asynchronous preset figure 2-12 ? timing model of registered i/o buffers with asynchronous preset inbuf inbuf tribuf clkbuf inbuf clkbuf data input i/o register with: active high preset positive-edge triggered data output register and enable output register with: active high preset postive-edge triggered pad out clk preset data_out data eout dout clk dq dfn1p1 pre dq dfn1p1 pre dq dfn1p1 pre d_enable a c d e f h i j l y core array
igloo nano dc and switching characteristics 2-42 revision 17 table 2-70 ? parameter definition and measuring nodes parameter name parameter definition measuring nodes (from, to)* t oclkq clock-to-q of the output data register h, dout t osud data setup time for the output data register f, h t ohd data hold time for the output data register f, h t opre2q asynchronous preset-to-q of the output data register l, dout t orempre asynchronous preset removal time for the output data register l, h t orecpre asynchronous preset recovery time for the output data register l, h t oeclkq clock-to-q of the output enable register h, eout t oesud data setup time for the output enable register j, h t oehd data hold time for the output enable register j, h t oepre2q asynchronous preset-to-q of the output enable register i, eout t oerempre asynchronous preset removal time for the output enable register i, h t oerecpre asynchronous preset recovery time for the output enable register i, h t iclkq clock-to-q of the input data register a, e t isud data setup time for the input data register c, a t ihd data hold time for the input data register c, a t ipre2q asynchronous preset-to-q of th e input data register d, e t irempre asynchronous preset removal time for the input data register d, a t irecpre asynchronous preset recovery time for the input data register d, a note: *see figure 2-12 on page 2-41 for more information.
igloo nano low power flash fpgas revision 17 2-43 fully registered i/o buff ers with asynchronous clear figure 2-13 ? timing model of the registered i/o buffers with asynchronous clear clk pad out clk clr data_out data y aa eout dout core array dq dfn1c1 clr dq dfn1c1 clr dq dfn1c1 clr d_enable cc dd ee ff ll hh jj clkbuf inbuf tribuf inbuf clkbuf inbuf data input i/o register with active high clear positive-edge triggered data output register and enable output register with active high clear positive-edge triggered
igloo nano dc and switching characteristics 2-44 revision 17 table 2-71 ? parameter definition and measuring nodes parameter name parameter definition measuring nodes (from, to)* t oclkq clock-to-q of the output data register hh, dout t osud data setup time for the output data register ff, hh t ohd data hold time for the output data register ff, hh t oclr2q asynchronous clear-to-q of the output data register ll, dout t oremclr asynchronous clear removal time for the output data register ll, hh t orecclr asynchronous clear recovery time for the output data register ll, hh t oeclkq clock-to-q of the output enable register hh, eout t oesud data setup time for the ou tput enable register jj, hh t oehd data hold time for the output enable register jj, hh t oeclr2q asynchronous clear-to-q of the output enable register ii, eout t oeremclr asynchronous clear removal time fo r the output enable register ii, hh t oerecclr asynchronous clear recovery time for the output enable register ii, hh t iclkq clock-to-q of the input data register aa, ee t isud data setup time for the input data register cc, aa t ihd data hold time for the input data register cc, aa t iclr2q asynchronous clear-to-q of the input data register dd, ee t iremclr asynchronous clear removal time for the input data register dd, aa t irecclr asynchronous clear recovery time for the input data register dd, aa note: *see figure 2-13 on page 2-43 for more information.
igloo nano low power flash fpgas revision 17 2-45 input register timing characteristics 1.5 v dc core voltage figure 2-14 ? input register timing diagram 50% clear out_1 clk data preset 50% t isud t ihd 50% 50% t iclkq 1 0 t irecpre t irempre t irecclr t iremclr t iwclr t iwpre t ipre2q t iclr2q t ickmpwh t ickmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-72 ? input data register propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description std. units t iclkq clock-to-q of the input data register 0.42 ns t isud data setup time for the input data register 0.47 ns t ihd data hold time for the input data register 0.00 ns t iclr2q asynchronous clear-to-q of the input data register 0.79 ns t ipre2q asynchronous preset-to-q of th e input data register 0.79 ns t iremclr asynchronous clear removal time for the input data register 0.00 ns t irecclr asynchronous clear recovery time for the input data register 0.24 ns t irempre asynchronous preset removal time for the input data register 0.00 ns t irecpre asynchronous preset recovery time for the input data register 0.24 ns t iwclr asynchronous clear minimum pulse widt h for the input data register 0.19 ns t iwpre asynchronous preset minimum pulse widt h for the input data register 0.19 ns t ickmpwh clock minimum pulse width high for the input data register 0.31 ns t ickmpwl clock minimum pulse width low for the input data register 0.28 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo nano dc and switching characteristics 2-46 revision 17 1.2 v dc core voltage table 2-73 ? input data register propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description std. units t iclkq clock-to-q of the input data register 0.68 ns t isud data setup time for the input data register 0.97 ns t ihd data hold time for the input data register 0.00 ns t iclr2q asynchronous clear-to-q of the input data register 1.19 ns t ipre2q asynchronous preset-to-q of th e input data register 1.19 ns t iremclr asynchronous clear removal time for the input data register 0.00 ns t irecclr asynchronous clear recovery time for the input data register 0.24 ns t irempre asynchronous preset removal time for the input data register 0.00 ns t irecpre asynchronous preset recovery time for the input data register 0.24 ns t iwclr asynchronous clear minimum pulse widt h for the input data register 0.19 ns t iwpre asynchronous preset minimum pulse widt h for the input data register 0.19 ns t ickmpwh clock minimum pulse width high for the input data register 0.31 ns t ickmpwl clock minimum pulse width low for the input data register 0.28 ns note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo nano low power flash fpgas revision 17 2-47 output register timing characteristics 1.5 v dc core voltage figure 2-15 ? output register timing diagram clear dout clk data_out preset 50% t osud t ohd 50% 50% t oclkq 1 0 t orecpre t orempre t orecclr t oremclr t owclr t owpre t opre2q t oclr2q t ockmpwh t ockmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-74 ? output data register propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description std. units t oclkq clock-to-q of the output data register 1.00 ns t osud data setup time for the ou tput data register 0.51 ns t ohd data hold time for the output data register 0.00 ns t oclr2q asynchronous clear-to-q of the output data register 1.34 ns t opre2q asynchronous preset-to-q of t he output data register 1.34 ns t oremclr asynchronous clear removal time fo r the output data register 0.00 ns t orecclr asynchronous clear recovery time for the output data register 0.24 ns t orempre asynchronous preset removal time for the output data register 0.00 ns t orecpre asynchronous preset recovery time for the output data register 0.24 ns t owclr asynchronous clear minimum pulse width for the output data register 0.19 ns t owpre asynchronous preset minimum pulse widt h for the output data register 0.19 ns t ockmpwh clock minimum pulse width high fo r the output data register 0.31 ns t ockmpwl clock minimum pulse width low for the output data register 0.28 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo nano dc and switching characteristics 2-48 revision 17 1.2 v dc core voltage table 2-75 ? output data register propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description std. units t oclkq clock-to-q of the output data register 1.52 ns t osud data setup time for the ou tput data register 1.15 ns t ohd data hold time for the output data register 0.00 ns t oclr2q asynchronous clear-to-q of the output data register 1.96 ns t opre2q asynchronous preset-to-q of t he output data register 1.96 ns t oremclr asynchronous clear removal time fo r the output data register 0.00 ns t orecclr asynchronous clear recovery time for the output data register 0.24 ns t orempre asynchronous preset removal time for the output data register 0.00 ns t orecpre asynchronous preset recovery time for the output data register 0.24 ns t owclr asynchronous clear minimum pulse width for the output data register 0.19 ns t owpre asynchronous preset minimum pulse widt h for the output data register 0.19 ns t ockmpwh clock minimum pulse width high fo r the output data register 0.31 ns t ockmpwl clock minimum pulse width low for the output data register 0.28 ns note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo nano low power flash fpgas revision 17 2-49 output enable register timing characteristics 1.5 v dc core voltage figure 2-16 ? output enable register timing diagram 50% preset clear eout clk d_enable 50% t oesud t oehd 50% 50% t oeclkq 1 0 t oerecpre t oerempre t oerecclr t oeremclr t oewclr t oewpre t oepre2q t oeclr2q t oeckmpwh t oeckmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-76 ? output enable register propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description std. units t oeclkq clock-to-q of the output enable register 0.75 ns t oesud data setup time for the output enable register 0.51 ns t oehd data hold time for the output enable register 0.00 ns t oeclr2q asynchronous clear-to-q of the output enable register 1.13 ns t oepre2q asynchronous preset-to-q of the output enable register 1.13 ns t oeremclr asynchronous clear removal time for the output enable register 0.00 ns t oerecclr asynchronous clear recovery time for the output enable register 0.24 ns t oerempre asynchronous preset removal time for the output enable register 0.00 ns t oerecpre asynchronous preset recovery time for the output enable register 0.24 ns t oewclr asynchronous clear minimum pulse width for the output enable register 0.19 ns t oewpre asynchronous preset minimum pulse width for the output enable register 0.19 ns t oeckmpwh clock minimum pulse width high for the output enable register 0.31 ns t oeckmpwl clock minimum pulse width low for the output enable register 0.28 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo nano dc and switching characteristics 2-50 revision 17 1.2 v dc core voltage table 2-77 ? output enable register propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description std. units t oeclkq clock-to-q of the output enable register 1.10 ns t oesud data setup time for the output enable register 1.15 ns t oehd data hold time for the output enable register 0.00 ns t oeclr2q asynchronous clear-to-q of the output enable register 1.65 ns t oepre2q asynchronous preset-to-q of the output enable register 1.65 ns t oeremclr asynchronous clear removal time for the output enable register 0.00 ns t oerecclr asynchronous clear recovery time for the output enable register 0.24 ns t oerempre asynchronous preset removal time for the output enable register 0.00 ns t oerecpre asynchronous preset recovery time for the output enable register 0.24 ns t oewclr asynchronous clear minimum pulse width for the output enable register 0.19 ns t oewpre asynchronous preset minimum pulse width for the output enable register 0.19 ns t oeckmpwh clock minimum pulse width high for the output enable register 0.31 ns t oeckmpwl clock minimum pulse width low for the output enable register 0.28 ns note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo nano low power flash fpgas revision 17 2-51 ddr module specifications note: ddr is not supported for agln010, agln015, and agln020 devices. input ddr module figure 2-17 ? input ddr timing model table 2-78 ? parameter definitions parameter name parameter definition measuring nodes (from, to) t ddriclkq1 clock-to-out out_qr b, d t ddriclkq2 clock-to-out out_qf b, e t ddrisud data setup time of ddr input a, b t ddrihd data hold time of ddr input a, b t ddriclr2q1 clear-to-out out_qr c, d t ddriclr2q2 clear-to-out out_qf c, e t ddriremclr clear removal c, b t ddrirecclr clear recovery c, b input ddr data clk clkbuf inbuf out_qf (to core) ff2 ff1 inbuf clr ddr_in e a b c d out_qr (to core)
igloo nano dc and switching characteristics 2-52 revision 17 timing characteristics 1.5 v dc core voltage figure 2-18 ? input ddr timing diagram t ddriclr2q2 t ddriremclr t ddrirecclr t ddriclr2q1 12 3 4 5 6 7 8 9 clk data clr out_qr out_qf t ddriclkq1 2 4 6 3 5 7 t ddrihd t ddrisud t ddriclkq2 table 2-79 ? input ddr propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.25 v parameter description std. units t ddriclkq1 clock-to-out out_qr for input ddr 0.48 ns t ddriclkq2 clock-to-out out_qf for input ddr 0.65 ns t ddrisud1 data setup for input ddr (negedge) 0.50 ns t ddrisud2 data setup for input ddr (posedge) 0.40 ns t ddrihd1 data hold for input ddr (negedge) 0.00 ns t ddrihd2 data hold for input ddr (posedge) 0.00 ns t ddriclr2q1 asynchronous clear-to-out out_qr for input ddr 0.82 ns t ddriclr2q2 asynchronous clear-to-out ou t_qf for input ddr 0.98 ns t ddriremclr asynchronous clear removal time for input ddr 0.00 ns t ddrirecclr asynchronous clear recovery time for input ddr 0.23 ns t ddriwclr asynchronous clear minimum pulse width for input ddr 0.19 ns t ddrickmpwh clock minimum pulse width high for input ddr 0.31 ns t ddrickmpwl clock minimum pulse width low for input ddr 0.28 ns f ddrimax maximum frequency for input ddr 250.00 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo nano low power flash fpgas revision 17 2-53 1.2 v dc core voltage table 2-80 ? input ddr propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description std. units t ddriclkq1 clock-to-out out_qr for input ddr 0.76 ns t ddriclkq2 clock-to-out out_qf for input ddr 0.94 ns t ddrisud1 data setup for input ddr (negedge) 0.93 ns t ddrisud2 data setup for input ddr (posedge) 0.84 ns t ddrihd1 data hold for input ddr (negedge) 0.00 ns t ddrihd2 data hold for input ddr (posedge) 0.00 ns t ddriclr2q1 asynchronous clear-to-out out_qr for input ddr 1.23 ns t ddriclr2q2 asynchronous clear-to-out ou t_qf for input ddr 1.42 ns t ddriremclr asynchronous clear removal time for input ddr 0.00 ns t ddrirecclr asynchronous clear recovery time for input ddr 0.24 ns t ddriwclr asynchronous clear minimum pulse width for input ddr 0.19 ns t ddrickmpwh clock minimum pulse width high for input ddr 0.31 ns t ddrickmpwl clock minimum pulse width low for input ddr 0.28 ns f ddrimax maximum frequency for input ddr 160.00 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo nano dc and switching characteristics 2-54 revision 17 output ddr module figure 2-19 ? output ddr timing model table 2-81 ? parameter definitions parameter name parameter defini tion measuring no des (from, to) t ddroclkq clock-to-out b, e t ddroclr2q asynchronous clear-to-out c, e t ddroremclr clear removal c, b t ddrorecclr clear recovery c, b t ddrosud1 data setup data_f a, b t ddrosud2 data setup data_r d, b t ddrohd1 data hold data_f a, b t ddrohd2 data hold data_r d, b data_f (from core) clk clkbuf out ff2 inbuf clr ddr_out output ddr ff1 0 1 x x x x x x x a b d e c c b outbuf data_r (from core)
igloo nano low power flash fpgas revision 17 2-55 timing characteristics 1.5 v dc core voltage figure 2-20 ? output ddr timing diagram 11 6 1 7 2 8 3 910 45 28 3 9 t ddroremclr t ddrohd1 t ddroremclr t ddrohd2 t ddrosud2 t ddroclkq t ddrorecclr clk data_r data_f clr out t ddroclr2q 710 4 table 2-82 ? output ddr propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description std. units t ddroclkq clock-to-out of ddr for output ddr 1.07 ns t ddrosud1 data_f data setup for output ddr 0.67 ns t ddrosud2 data_r data setup for output ddr 0.67 ns t ddrohd1 data_f data hold for output ddr 0.00 ns t ddrohd2 data_r data hold for output ddr 0.00 ns t ddroclr2q asynchronous clear-to-out for output ddr 1.38 ns t ddroremclr asynchronous clear removal time for output ddr 0.00 ns t ddrorecclr asynchronous clear recovery time for output ddr 0.23 ns t ddrowclr1 asynchronous clear minimum pulse width for output ddr 0.19 ns t ddrockmpwh clock minimum pulse width high for the output ddr 0.31 ns t ddrockmpwl clock minimum pulse width low for the output ddr 0.28 ns f ddomax maximum frequency for the output ddr 250.00 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo nano dc and switching characteristics 2-56 revision 17 1.2 v dc core voltage table 2-83 ? output ddr propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description std. units t ddroclkq clock-to-out of ddr for output ddr 1.60 ns t ddrosud1 data_f data setup for output ddr 1.09 ns t ddrosud2 data_r data setup for output ddr 1.16 ns t ddrohd1 data_f data hold for output ddr 0.00 ns t ddrohd2 data_r data hold for output ddr 0.00 ns t ddroclr2q asynchronous clear-to-out for output ddr 1.99 ns t ddroremclr asynchronous clear removal time for output ddr 0.00 ns t ddrorecclr asynchronous clear recovery time for output ddr 0.24 ns t ddrowclr1 asynchronous clear minimum pulse width for output ddr 0.19 ns t ddrockmpwh clock minimum pulse width high for the output ddr 0.31 ns t ddrockmpwl clock minimum pulse width low for the output ddr 0.28 ns f ddomax maximum frequency for the output ddr 160.00 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo nano low power flash fpgas revision 17 2-57 versatile characteristics versatile specifications as a combinatorial module the igloo nano library offers all co mbinations of lut-3 combinatorial functions. in this section, timing characteristics are presented for a sample of the library. for more details, refer to the fusion, igloo/e, and proasic3/ e macro library guide . figure 2-21 ? sample of combinatorial cells maj3 a c by mux2 b 0 1 a s y ay b b a xor2 y nor2 b a y b a y or2 inv a y and2 b a y nand3 b a c xor3 y b a c nand2
igloo nano dc and switching characteristics 2-58 revision 17 figure 2-22 ? timing model and waveforms net a y b length = 1 versatile net a y b length = 1 versatile net a y b length = 1 versatile net a y b length = 1 versatile nand2 or any combinatorial logic nand2 or any combinatorial logic nand2 or any combinatorial logic nand2 or any combinatorial logic t pd = max(t pd(rr) , t pd(rf) , t pd(ff) , t pd(fr) ) where edges are applicable for a particular combinatorial cell fanout = 4 t pd t pd t pd 50% vcc vcc vcc 50% gnd a, b, c 50% 50% 50% (rr) (rf) gnd out out gnd 50% (ff) (fr) t pd t pd
igloo nano low power flash fpgas revision 17 2-59 timing characteristics 1.5 v dc core voltage 1.2 v dc core voltage table 2-84 ? combinatorial cell propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v combinatorial cell equation parameter std. units inv y = !a t pd 0.76 ns and2 y = a b t pd 0.87 ns nand2 y = !(a b) t pd 0.91 ns or2 y = a + b t pd 0.90 ns nor2 y = !(a + b) t pd 0.94 ns xor2 y = a ?? bt pd 1.39 ns maj3 y = maj(a, b, c) t pd 1.44 ns xor3 y = a ? b ?? ct pd 1.60 ns mux2 y = a !s + b s t pd 1.17 ns and3 y = a b c t pd 1.18 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-85 ? combinatorial cell propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v combinatorial cell equation parameter std. units inv y = !a t pd 1.33 ns and2 y = a b t pd 1.48 ns nand2 y = !(a b) t pd 1.58 ns or2 y = a + b t pd 1.53 ns nor2 y = !(a + b) t pd 1.63 ns xor2 y = a ?? bt pd 2.34 ns maj3 y = maj(a, b, c) t pd 2.59 ns xor3 y = a ? b ?? ct pd 2.74 ns mux2 y = a !s + b s t pd 2.03 ns and3 y = a b c t pd 2.11 ns note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo nano dc and switching characteristics 2-60 revision 17 versatile specifications as a sequential module the igloo nano library offers a wide variety of sequen tial cells, including flip-flops and latches. each has a data input and optional enable, clear, or preset. in this section, timing characteristics are presented for a representative sample from the library. for more details, refer to the fusion, igloo/e, and proasic3/e macro library guide . figure 2-23 ? sample of sequential cells dq dfn1 data clk out d q dfn1c1 data clk out clr dq dfi1e1p1 data clk out en pre d q dfn1e1 data clk out en
igloo nano low power flash fpgas revision 17 2-61 timing characteristics 1.5 v dc core voltage figure 2-24 ? timing model and waveforms pre clr out clk data en t sue 50% 50% t sud t hd 50% 50% t clkq 0 t he t recpre t rempre t recclr t remclr t wclr t wpre t pre2q t clr2q t ckmpwh t ckmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-86 ? register delays commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description std. units t clkq clock-to-q of the core register 0.89 ns t sud data setup time for the core register 0.81 ns t hd data hold time for the core register 0.00 ns t sue enable setup time for the core register 0.73 ns t he enable hold time for the core register 0.00 ns t clr2q asynchronous clear-to-q of the core register 0.60 ns t pre2q asynchronous preset-to-q of the core register 0.62 ns t remclr asynchronous clear removal time for the core register 0.00 ns t recclr asynchronous clear recovery time for the core register 0.24 ns t rempre asynchronous preset removal time for the core register 0.00 ns t recpre asynchronous preset recovery time for the core register 0.23 ns t wclr asynchronous clear minimum pulse width for the core register 0.30 ns t wpre asynchronous preset minimum pulse width for the core register 0.30 ns t ckmpwh clock minimum pulse width high for the core register 0.56 ns t ckmpwl clock minimum pulse width low for the core register 0.56 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo nano dc and switching characteristics 2-62 revision 17 1.2 v dc core voltage table 2-87 ? register delays commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description std. units t clkq clock-to-q of the core register 1.61 ns t sud data setup time for the core register 1.17 ns t hd data hold time for the core register 0.00 ns t sue enable setup time for the core register 1.29 ns t he enable hold time for the core register 0.00 ns t clr2q asynchronous clear-to-q of the core register 0.87 ns t pre2q asynchronous preset-to-q of the core register 0.89 ns t remclr asynchronous clear removal time for the core register 0.00 ns t recclr asynchronous clear recovery time for the core register 0.24 ns t rempre asynchronous preset removal time for the core register 0.00 ns t recpre asynchronous preset recovery time for the core register 0.24 ns t wclr asynchronous clear minimum pulse width for the core register 0.46 ns t wpre asynchronous preset minimum pulse width for the core register 0.46 ns t ckmpwh clock minimum pulse width high for the core register 0.95 ns t ckmpwl clock minimum pulse width low for the core register 0.95 ns note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo nano low power flash fpgas revision 17 2-63 global resource characteristics agln125 clock tree topology clock delays are device-specific. figure 2-25 is an example of a global tree used for clock routing. the global tree presented in figure 2-25 is driven by a ccc located on the west side of the agln125 device. it is used to drive all d- flip-flops in the device. figure 2-25 ? example of global tree use in an agln125 device for clock routing central global rib versatile rows global spine ccc
igloo nano dc and switching characteristics 2-64 revision 17 global tree timing characteristics global clock delays include the central rib delay, the spine delay, and the row delay. delays do not include i/o input buffer clock delays, as these are i/o standard?dependent, and the clock may be driven and conditioned internally by the ccc module. for more details on clock conditioning capabilities, refer to the "clock conditioning circuits" section on page 2-70 . ta b l e 2 - 8 8 to table 2-96 on page 2-68 present minimum and maximum global clock delays within each device. minimum and maximum delays are measured with minimum and maximum loading. timing characteristics 1.5 v dc core voltage table 2-88 ? agln010 global resource commercial-case conditions: t j = 70c, vcc = 1.425 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 1.13 1.42 ns t rckh input high delay for global clock 1.15 1.50 ns t rckmpwh minimum pulse width high for global clock 1.40 ns t rckmpwl minimum pulse width low for global clock 1.65 ns t rcksw maximum skew for global clock 0.35 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-89 ? agln015 global resource commercial-case conditions: t j = 70c, vcc = 1.425 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 1.21 1.55 ns t rckh input high delay for global clock 1.23 1.65 ns t rckmpwh minimum pulse width high for global clock 1.40 ns t rckmpwl minimum pulse width low for global clock 1.65 ns t rcksw maximum skew for global clock 0.42 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo nano low power flash fpgas revision 17 2-65 table 2-90 ? agln020 global resource commercial-case conditions: t j = 70c, vcc = 1.425 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 1.21 1.55 ns t rckh input high delay for global clock 1.23 1.65 ns t rckmpwh minimum pulse width high for global clock 1.40 ns t rckmpwl minimum pulse width low for global clock 1.65 ns t rcksw maximum skew for global clock 0.42 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-91 ? agln060 global resource commercial-case conditions: t j = 70c, vcc = 1.425 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 1.32 1.62 ns t rckh input high delay for global clock 1.34 1.71 ns t rckmpwh minimum pulse width high for global clock 1.40 ns t rckmpwl minimum pulse width low for global clock 1.65 ns t rcksw maximum skew for global clock 0.38 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo nano dc and switching characteristics 2-66 revision 17 table 2-92 ? agln125 global resource commercial-case conditions: t j = 70c, vcc = 1.425 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 1.36 1.71 ns t rckh input high delay for global clock 1.39 1.82 ns t rckmpwh minimum pulse width high for global clock 1.40 ns t rckmpwl minimum pulse width low for global clock 1.65 ns t rcksw maximum skew for global clock 0.43 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-93 ? agln250 global resource commercial-case conditions: t j = 70c, vcc = 1.425 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 1.39 1.73 ns t rckh input high delay for global clock 1.41 1.84 ns t rckmpwh minimum pulse width high for global clock 1.40 ns t rckmpwl minimum pulse width low for global clock 1.65 ns t rcksw maximum skew for global clock 0.43 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo nano low power flash fpgas revision 17 2-67 1.2 v dc core voltage table 2-94 ? agln010 global resource commercial-case conditions: t j = 70c, vcc = 1.14 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 1.71 2.09 ns t rckh input high delay for global clock 1.78 2.31 ns t rckmpwh minimum pulse width high for global clock 1.40 ns t rckmpwl minimum pulse width low for global clock 1.65 ns t rcksw maximum skew for global clock 0.53 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values. table 2-95 ? agln015 global resource commercial-case conditions: t j = 70c, vcc = 1.14 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 1.81 2.26 ns t rckh input high delay for global clock 1.90 2.51 ns t rckmpwh minimum pulse width high for global clock 1.40 ns t rckmpwl minimum pulse width low for global clock 1.65 ns t rcksw maximum skew for global clock 0.61 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo nano dc and switching characteristics 2-68 revision 17 table 2-96 ? agln020 global resource commercial-case conditions: t j = 70c, vcc = 1.14 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 1.81 2.26 ns t rckh input high delay for global clock 1.90 2.51 ns t rckmpwh minimum pulse width high for global clock 1.40 ns t rckmpwl minimum pulse width low for global clock 1.65 ns t rcksw maximum skew for global clock 0.61 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values. table 2-97 ? agln060 global resource commercial-case conditions: t j = 70c, vcc = 1.14 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 2.02 2.42 ns t rckh input high delay for global clock 2.09 2.65 ns t rckmpwh minimum pulse width high for global clock 1.40 ns t rckmpwl minimum pulse width low for global clock 1.65 ns t rcksw maximum skew for global clock 0.56 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo nano low power flash fpgas revision 17 2-69 table 2-98 ? agln125 global resource commercial-case conditions: t j = 70c, vcc = 1.14 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 2.08 2.54 ns t rckh input high delay for global clock 2.15 2.77 ns t rckmpwh minimum pulse width high for global clock 1.40 ns t rckmpwl minimum pulse width low for global clock 1.65 ns t rcksw maximum skew for global clock 0.62 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values. table 2-99 ? agln250 global resource commercial-case conditions: t j = 70c, vcc = 1.14 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 2.11 2.57 ns t rckh input high delay for global clock 2.19 2.81 ns t rckmpwh minimum pulse width high for global clock 1.40 ns t rckmpwl minimum pulse width low for global clock 1.65 ns t rcksw maximum skew for global clock 0.62 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo nano dc and switching characteristics 2-70 revision 17 clock conditioning circuits ccc electrical specifications timing characteristics table 2-100 ? igloo nano ccc/pll specification for igloo nano v2 or v5 devices, 1.5 v dc core supply voltage parameter min. typ. max. units clock conditioning circuitry input frequency f in_ccc 1.5 250 mhz clock conditioning circuitry output frequency f out_ccc 0.75 250 mhz delay increments in programmable delay blocks 1, 2 360 3 ps number of programmable values in each programmable delay block 32 serial clock (sclk) for dynamic pll 4,9 100 mhz input cycle-to-cycle jitter (peak magnitude) 1 ns acquisition time lockcontrol = 0 300 s lockcontrol = 1 6.0 ms tracking jitter 5 lockcontrol = 0 2.5 ns lockcontrol = 1 1.5 ns output duty cycle 48.5 51.5 % delay range in block: programmable delay 1 1, 2 1.25 15.65 ns delay range in block: programmable delay 2 1, 2, 0.025 15.65 ns delay range in block: fixed delay 1, 2 3.5 ns vco output peak-to-peak period jitter f ccc_out 6 max peak-to-peak jitter data 6,7,8 sso ? 2 sso ? 4 sso ? 8sso ? 16 0.75 mhz to 50 mhz 0.50 0.60 0.80 1.20 % 50 mhz to 250 mhz 2.50 4.00 6.00 12.00 % notes: 1. this delay is a function of voltage and temperature. see table 2-6 on page 2-6 and table 2-7 on page 2-7 for deratings. 2. t j = 25c, v cc = 1.5 v 3. when the ccc/pll core is generated by microsemi core generator software, not all delay values of the specified delay increments are available. refer to the libero soc online help associated with the core for more information. 4. maximum value obtained for a std speed grade device in worst-case commercial conditions. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 and table 2-7 on page 2-7 for derating values. 5. tracking jitter is defined as the variation in clock edge position of pll outputs with reference to pll input clock edge. tracking jitter does not measure the variation in pll output period, which is covered by the period jitter parameter. 6. vco output jitter is calculated as a percentage of the vco frequency. the jitter (in ps) can be calculated by multiplying the vco period by the % jitter. the vco jitter (in ps) applies to ccc_out, regardless of the output divider settings. for example, if the jitter on vco is 300 ps, the jitter on ccc_out is also 300 ps, no matter what the settings are for the output divider. 7. measurements done with lvttl 3.3 v 8 ma i/o drive strength and high slew rate. vcc/vccpll = 1.425 v, vcci = 3.3 v, vq/pq/tq type of packages, 20 pf load. 8. ssos are outputs that are synchronous to a single clock domain and have their clock-to-out times within 200 ps of each other. switching i/os are placed outside of the pll bank. refer to the "simultaneously switching outputs (ssos) and printed circuit board layout" section in the igloo nano fpga fabric user?s guide . 9. the agln010, agln015, and agln 020 devices do not support plls.
igloo nano low power flash fpgas revision 17 2-71 table 2-101 ? igloo nano ccc/pll specification for igloo nano v2 devices, 1.2 v dc core supply voltage parameter min. typ. max. units clock conditioning circuitry input frequency f in_ccc 1.5 160 mhz clock conditioning circuitry output frequency f out_ccc 0.75 160 mhz delay increments in programmable delay blocks 1, 2 580 3 ps number of programmable values in each programmable delay block 32 serial clock (sclk) for dynamic pll 4,9 60 input cycle-to-cycle jitter (peak magnitude) 0.25 ns acquisition time lockcontrol = 0 300 s lockcontrol = 1 6.0 ms tracking jitter 5 lockcontrol = 0 4 ns lockcontrol = 1 3 ns output duty cycle 48.5 51.5 % delay range in block: programmable delay 1 1, 2 2.3 20.86 ns delay range in block: programmable delay 2 1, 2 0.025 20.86 ns delay range in block: fixed delay 1, 2 5.7 ns vco output peak-to-peak period jitter f ccc_out 6 max peak-to-peak period jitter 6,7,8 sso ? 2sso ? 4 sso ? 8sso ? 16 0.75 mhz to 50mhz 0.50 1.20 2.00 3.00 % 50 mhz to 100 mhz 2.50 5.00 7.00 15.00 % notes: 1. this delay is a function of voltage and temperature. see table 2-6 on page 2-6 and table 2-7 on page 2-7 for deratings. 2. t j = 25c, v cc = 1.2 v. 3. when the ccc/pll core is generated by microsemi core generator software, not all delay values of the specified delay increments are available. refer to the libero soc online help associated with the core for more information. 4. maximum value obtained for a std speed grade device in worst-case commercial conditions. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 and table 2-7 on page 2-7 for derating values. 5. tracking jitter is defined as the variation in clock edge position of pll outputs with reference to the pll input clock edge. tracking jitter does not measure the variation in pll output period, which is covered by the period jitter parameter. 6. vco output jitter is calculated as a percentage of the vco frequency. the jitter (in ps) can be calculated by multiplying the vco period by the % jitter. the vco jitter (in ps) applies to ccc_out, regard less of the output di vider settings. for example, if the jitter on vco is 300 ps, the jitter on ccc_out is also 300 ps, no matter what the settings are for the output divider. 7. measurements done with lvttl 3.3 v 8 ma i/o drive strength and high slew rate. vcc/vccpll = 1.14 v, vcci = 3.3 v, vq/pq/tq type of packages, 20 pf load. 8. ssos are outputs that are synchronous to a single clock domain and have their clock-to-out times within 200 ps of each other. switching i/os are placed outside of the pll bank. refer to the "simultaneously switching outputs (ssos) and printed circuit board layout" section in the igloo nano fpga fabric user?s guide . 9. the agln010, agln015, and agln 020 devices do not support plls.
igloo nano dc and switching characteristics 2-72 revision 17 note: peak-to-peak jitter meas urements are defined by t peak-to-peak = t period_max ? t period_min . figure 2-26 ? peak-to-peak jitter definition t period_max t period_min output signal
igloo nano low power flash fpgas revision 17 2-73 embedded sram and fifo characteristics sram figure 2-27 ? ram models addra11 douta8 douta7 douta0 doutb8 doutb7 doutb0 addra10 addra0 dina8 dina7 dina0 widtha1 widtha0 pipea wmodea blka wena clka addrb11 addrb10 addrb0 dinb8 dinb7 dinb0 widthb1 widthb0 pipeb wmodeb blkb wenb clkb ram4k9 raddr8 rd17 raddr7 rd16 raddr0 rd0 wd17 wd16 wd0 ww1 ww0 rw1 rw0 pipe ren rclk ram512x18 waddr8 waddr7 waddr0 wen wclk reset reset
igloo nano dc and switching characteristics 2-74 revision 17 timing waveforms figure 2-28 ? ram read for pass-through output. applicable to both ram4k9 and ram512x18. figure 2-29 ? ram read for pipelined output. appl icable to both ram4k9 and ram512x18. clk [r|w]addr blk wen dout|rd a 0 a 1 a 2 d 0 d 1 d 2 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh1 t bkh d n t ckq1 clk [r|w]addr blk wen dout|rd a 0 a 1 a 2 d 0 d 1 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh2 t ckq2 t bkh d n
igloo nano low power flash fpgas revision 17 2-75 figure 2-30 ? ram write, output retained (wmode = 0) . applicable to both ram4k9 and ram512x18. figure 2-31 ? ram write, output as write data (wmode = 1). applicable to ram4k9 only. t cyc t ckh t ckl a 0 a 1 a 2 di 0 di 1 t as t ah t bks t ens t enh t ds t dh clk blk wen [r|w]addr din|wd d n dout|rd t bkh d 2 t cyc t ckh t ckl a 0 a 1 a 2 di 0 di 1 t as t ah t bks t ens t ds t dh clk blk wen addr din t bkh dout (pass-through) di 1 d n di 0 dout (pipelined) di 0 di 1 d n di 2
igloo nano dc and switching characteristics 2-76 revision 17 figure 2-32 ? ram reset. applicable to both ram4k9 and ram512x18. clk reset dout|rd d n t cyc t ckh t ckl t rstbq d m
igloo nano low power flash fpgas revision 17 2-77 timing characteristics 1.5 v dc core voltage table 2-102 ? ram4k9 commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description std. units t as address setup time 0.69 ns t ah address hold time 0.13 ns t ens ren, wen setup time 0.68 ns t enh ren, wen hold time 0.13 ns t bks blk setup time 1.37 ns t bkh blk hold time 0.13 ns t ds input data (din) setup time 0.59 ns t dh input data (din) hold time 0.30 ns t ckq1 clock high to new data valid on dout (output retained, wmode = 0) 2.94 ns clock high to new data valid on dout (flow-through, wmode = 1) 2.55 ns t ckq2 clock high to new data valid on dout (pipelined) 1.51 ns t c2cwwl 1 address collision clk-to-clk delay for reliable write after write on same address; applicable to closing edge 0.23 ns t c2crwh 1 address collision clk-to-clk delay for reliabl e read access after write on same address; applicable to opening edge 0.35 ns t c2cwrh 1 address collision clk-to-clk delay for reliable write access after read on same address; applicable to opening edge 0.41 ns t rstbq reset low to data out low on dout (flow- through) 1.72 ns reset low to data out low on dout (pipelined) 1.72 ns t remrstb reset removal 0.51 ns t recrstb reset recovery 2.68 ns t mpwrstb reset minimum pulse width 0.68 ns t cyc clock cycle time 6.24 ns f max maximum frequency 160 mhz notes: 1. for more information, refer to the application note simultaneous read-write operations in dual-port sram for flash- based csocs and fpgas . 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo nano dc and switching characteristics 2-78 revision 17 table 2-103 ? ram512x18 commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description std. units t as address setup time 0.69 ns t ah address hold time 0.13 ns t ens ren, wen setup time 0.61 ns t enh ren, wen hold time 0.07 ns t ds input data (wd) setup time 0.59 ns t dh input data (wd) hold time 0.30 ns t ckq1 clock high to new data valid on rd (output retained) 3.51 ns t ckq2 clock high to new data valid on rd (pipelined) 1.43 ns t c2crwh 1 address collision clk-to-clk delay for reliabl e read access after write on same address; applicable to opening edge 0.35 ns t c2cwrh 1 address collision clk-to-clk delay for reliable write access after read on same address; applicable to opening edge 0.42 ns t rstbq reset low to data out low on rd (flow- through) 1.72 ns reset low to data out low on rd (pipelined) 1.72 ns t remrstb reset removal 0.51 0.51 t recrstb reset recovery 2.68 ns t mpwrstb reset minimum pulse width 0.68 ns t cyc clock cycle time 6.24 ns f max maximum frequency 160 mhz notes: 1. for more information, refer to the application note simultaneous read-write operations in dual-port sram for flash- based csocs and fpgas . 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo nano low power flash fpgas revision 17 2-79 1.2 v dc core voltage table 2-104 ? ram4k9 commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description std. units t as address setup time 1.28 ns t ah address hold time 0.25 ns t ens ren, wen setup time 1.25 ns t enh ren, wen hold time 0.25 ns t bks blk setup time 2.54 ns t bkh blk hold time 0.25 ns t ds input data (din) setup time 1.10 ns t dh input data (din) hold time 0.55 ns t ckq1 clock high to new data valid on dout (output retained, wmode = 0) 5.51 ns clock high to new data valid on dout (flow-through, wmode = 1) 4.77 ns t ckq2 clock high to new data valid on dout (pipelined) 2.82 ns t c2cwwl 1 address collision clk-to-clk delay for reliable write after write on same address; applicable to closing edge 0.30 ns t c2crwh 1 address collision clk-to-clk delay for reliable read access after write on same address; applicable to opening edge 0.89 ns t c2cwrh 1 address collision clk-to-clk delay for reliable write access after read on same address; applicable to opening edge 1.01 ns t rstbq reset low to data out low on dout (flow-through) 3.21 ns reset low to data out low on do (pipelined) 3.21 ns t remrstb reset removal 0.93 ns t recrstb reset recovery 4.94 ns t mpwrstb reset minimum pulse width 1.18 ns t cyc clock cycle time 10.90 ns f max maximum frequency 92 mhz notes: 1. for more information, refer to the application note simultaneous read-write operations in dual-port sram for flash- based csocs and fpgas . 2. for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo nano dc and switching characteristics 2-80 revision 17 table 2-105 ? ram512x18 commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description std. units t as address setup time 1.28 ns t ah address hold time 0.25 ns t ens ren, wen setup time 1.13 ns t enh ren, wen hold time 0.13 ns t ds input data (wd) setup time 1.10 ns t dh input data (wd) hold time 0.55 ns t ckq1 clock high to new data valid on rd (output retained) 6.56 ns t ckq2 clock high to new data valid on rd (pipelined) 2.67 ns t c2crwh 1 address collision clk-to-clk delay for reliable read access after write on same address; applicable to opening edge 0.87 ns t c2cwrh 1 address collision clk-to-clk delay for reliabl e write access after read on same address; applicable to opening edge 1.04 ns t rstbq reset low to data out low on rd (flow through) 3.21 ns reset low to data out low on rd (pipelined) 3.21 ns t remrstb reset removal 0.93 ns t recrstb reset recovery 4.94 ns t mpwrstb reset minimum pulse width 1.18 ns t cyc clock cycle time 10.90 ns f max maximum frequency 92 mhz notes: 1. for more information, refer to the application note simultaneous read-write operations in dual-port sram for flash- based csocs and fpgas . 2. for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo nano low power flash fpgas revision 17 2-81 fifo figure 2-33 ? fifo model fifo4k18 rw2 rd17 rw1 rd16 rw0 ww2 ww1 ww0 rd0 estop fstop full afull empty afval11 aempty afval10 afval0 aeval11 aeval10 aeval0 ren rblk rclk wen wblk wclk rpipe wd17 wd16 wd0 reset
igloo nano dc and switching characteristics 2-82 revision 17 timing waveforms figure 2-34 ? fifo read figure 2-35 ? fifo write t ens t enh t ckq1 t ckq2 t cyc d 0 d 1 d n d n d 0 d 2 d 1 t bks t bkh rclk rblk ren rd (flow-through) rd (pipelined) wclk wen wd t ens t enh t ds t dh t cyc di 0 di 1 t bkh t bks wblk
igloo nano low power flash fpgas revision 17 2-83 figure 2-36 ? fifo reset figure 2-37 ? fifo empty flag and aempty flag assertion match (a 0 ) t mpwrstb t rstfg t rstck t rstaf rclk/ wclk reset empty aempty wa/ra (address counter) t rstfg t rstaf full afull rclk no match no match dist = aef_th match (empty) t ckaf t rckef empty aempty t cyc wa/ra (address counter)
igloo nano dc and switching characteristics 2-84 revision 17 figure 2-38 ? fifo full flag and afull flag assertion figure 2-39 ? fifo empty flag and aempty flag deassertion figure 2-40 ? fifo full flag and afull flag deassertion no match no match dist = aff_th match (full) t ckaf t wckff t cyc wclk full afull wa/ra (address counter) wclk wa/ra (address counter) match (empty) no match no match no match dist = aef_th + 1 no match rclk empty 1st rising edge after 1st write 2nd rising edge after 1st write t rckef t ckaf aempty dist = aff_th ? 1 match (full) no match no match no match no match t wckf t ckaf 1st rising edge after 1st read 1st rising edge after 2nd read rclk wa/ra (address counter) wclk full afull
igloo nano low power flash fpgas revision 17 2-85 timing characteristics 1.5 v dc core voltage table 2-106 ? fifo worst commercial-case conditions: t j = 70c, vcc = 1.425 v parameter description std. units t ens ren, wen setup time 1.66 ns t enh ren, wen hold time 0.13 ns t bks blk setup time 0.30 ns t bkh blk hold time 0.00 ns t ds input data (wd) setup time 0.63 ns t dh input data (wd) hold time 0.20 ns t ckq1 clock high to new data valid on rd (flow-through) 2.77 ns t ckq2 clock high to new data valid on rd (pipelined) 1.50 ns t rckef rclk high to empty flag valid 2.94 ns t wckff wclk high to full flag valid 2.79 ns t ckaf clock high to almost empty/full flag valid 10.71 ns t rstfg reset low to empty/full flag valid 2.90 ns t rstaf reset low to almost empty/full flag valid 10.60 ns t rstbq reset low to data out low on rd (flow-through) 1.68 ns reset low to data out lo w on rd (pipelined) 1.68 ns t remrstb reset removal 0.51 ns t recrstb reset recovery 2.68 ns t mpwrstb reset minimum pulse width 0.68 ns t cyc clock cycle time 6.24 ns f max maximum frequency for fifo 160 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo nano dc and switching characteristics 2-86 revision 17 1.2 v dc core voltage table 2-107 ? fifo worst commercial-case conditions: t j = 70c, vcc = 1.14 v parameter description std. units t ens ren, wen setup time 3.44 ns t enh ren, wen hold time 0.26 ns t bks blk setup time 0.30 ns t bkh blk hold time 0.00 ns t ds input data (di) setup time 1.30 ns t dh input data (di) hold time 0.41 ns t ckq1 clock high to new data valid on rd (flow-through) 5.67 ns t ckq2 clock high to new data valid on rd (pipelined) 3.02 ns t rckef rclk high to empty flag valid 6.02 ns t wckff wclk high to full flag valid 5.71 ns t ckaf clock high to almost empty/full flag valid 22.17 ns t rstfg reset low to empty/full flag valid 5.93 ns t rstaf reset low to almost empty/full flag valid 21.94 ns t rstbq reset low to data out low on rd (flow-through) 3.41 ns reset low to data out low on rd (pipelined) 4.09 3.41 t remrstb reset removal 1.02 ns t recrstb reset recovery 5.48 ns t mpwrstb reset minimum pulse width 1.18 ns t cyc clock cycle time 10.90 ns f max maximum frequency for fifo 92 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo nano low power flash fpgas revision 17 2-87 embedded flashrom characteristics timing characteristics 1.5 v dc core voltage 1.2 v dc core voltage figure 2-41 ? timing diagram a 0 a 1 t su t hold t su t hold t su t hold t ckq2 t ckq2 t ckq2 clk a ddress data d 0 d 0 d 1 table 2-108 ? embedded flashrom access time worst commercial-case conditions: t j = 70c, vcc = 1.425 v parameter description std. units t su address setup time 0.57 ns t hold address hold time 0.00 ns t ck2q clock to out 20.90 ns f max maximum clock frequency 15 mhz table 2-109 ? embedded flashrom access time worst commercial-case conditions: t j = 70c, vcc = 1.14 v parameter description std. units t su address setup time 0.59 ns t hold address hold time 0.00 ns t ck2q clock to out 35.74 ns f max maximum clock frequency 10 mhz
jtag 1532 characteristics jtag timing delays do not include jtag i/os. to obtai n complete jtag timing, add i/o buffer delays to the corresponding standard selected; refer to the i/o timing characteristics in the "user i/o characteristics" section on page 2-15 for more details. timing characteristics 1.5 v dc core voltage 1.2 v dc core voltage table 2-110 ? jtag 1532 commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description std. units t disu test data input setup time 1.00 ns t dihd test data input hold time 2.00 ns t tmssu test mode select setup time 1.00 ns t tmdhd test mode select hold time 2.00 ns t tck2q clock to q (data out) 8.00 ns t rstb2q reset to q (data out) 25.00 ns f tckmax tck maximum frequency 15 mhz t trstrem resetb removal time 0.58 ns t trstrec resetb recovery time 0.00 ns t trstmpw resetb minimum pulse tbd ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-111 ? jtag 1532 commercial-case conditions: t j = 70c, worst-case vcc = 1.14 v parameter description std. units t disu test data input setup time 1.50 ns t dihd test data input hold time 3.00 ns t tmssu test mode select setup time 1.50 ns t tmdhd test mode select hold time 3.00 ns t tck2q clock to q (data out) 11.00 ns t rstb2q reset to q (data out) 30.00 ns f tckmax tck maximum frequency 9.00 mhz t trstrem resetb removal time 1.18 ns t trstrec resetb recovery time 0.00 ns t trstmpw resetb minimum pulse tbd ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
revision 17 3-1 3 ? pin descriptions supply pins gnd ground ground supply voltage to the core, i/o outputs, and i/o logic. gndq ground (quiet) quiet ground supply voltage to input buffers of i/o banks. within the package, the gndq plane is decoupled from the simultaneous switching noise orig inated from the output buffer ground domain. this minimizes the noise transfer within the package and im proves input signal integrity. gndq must always be connected to gnd on the board. vcc core supply voltage supply voltage to the fpga core, nominally 1.5 v fo r igloo nano v5 devices, and 1.2 v or 1.5 v for igloo nano v2 devices. vcc is required for poweri ng the jtag state machine in addition to vjtag. even when a device is in bypass mode in a jtag chai n of interconnected devices, both vcc and vjtag must remain powered to allow jtag signals to pass through the device. vccibx i/o supply voltage supply voltage to the bank's i/o output buffers and i/o logic. bx is the i/o bank number. there are up to eight i/o banks on low power flash devices plus a dedicated vjtag bank. each bank can have a separate vcci connection. all i/os in a bank will run off the same vccibx supply. vcci can be 1.2 v, 1.5 v, 1.8 v, 2.5 v, or 3.3 v, nominal voltage. un used i/o banks should have their corresponding vcci pins tied to gnd. vmvx i/o supply voltage (quiet) quiet supply voltage to the input buffers of each i/o bank. x is the bank number. within the package, the vmv plane biases the input stage of the i/os in the i/o banks. this minimizes the noise transfer within the package and improves input signal integrity. ea ch bank must have at least one vmv connection, and no vmv should be left unconnected. all i/os in a bank run off the same vmvx supply. vmv is used to provide a quiet supply voltage to the input buffer s of each i/o bank. vmvx can be 1.2 v, 1.5 v, 1.8 v, 2.5 v, or 3.3 v, nominal voltage. unused i/o banks shou ld have their corresponding vmv pins tied to gnd. vmv and vcci should be at the same voltage within a given i/o bank. used vmv pins must be connected to the corresponding vcci pins of the same bank (i.e., vmv0 to vccib0, vmv1 to vccib1, etc.). vccpla/b/c/d/e/f pll supply voltage supply voltage to analog pll, nominally 1.5 v or 1.2 v. when the plls are not used, the microsemi designer place-and-route tool automatically disables the unused plls to lower power consumption. the user should tie unused vccplx and vcomplx pins to ground. microsemi recommends tying vccplx to vcc and using proper filtering circuits to decouple vcc noise from the plls. refer to the pll power s upply decoupling section of the "clock conditioning circuits in igloo and proasic3 devices" chapter in the igloo nano fpga fabric user?s guide for a complete board solution for the pll analog power supply and ground. there is one vccplf pin on igloo nano devices. vcompla/b/c/d/e/f pll ground ground to analog pll power supplies. when the plls are not used, the microsemi designer place-and- route tool automatically disables the unused plls to lower power consumption. the user should tie unused vccplx and vcomplx pins to ground. there is one vcomplf pin on igloo nano devices. vjtag jtag supply voltage low power flash devices have a separate bank for the dedicated jtag pins. the jtag pins can be run at any voltage from 1.5 v to 3.3 v (nominal). isol ating the jtag power supply in a separate i/o bank gives greater flexibility in supply selection and si mplifies power supply and pcb design. if the jtag
pin descriptions 3-2 revision 17 interface is neither used nor planned for use, the vj tag pin together with the trst pin could be tied to gnd. it should be noted that vcc is required to be powered for jtag operation; vjtag alone is insufficient. if a device is in a jtag chain of in terconnected boards, the board containing the device can be powered down, provided both vjtag and vcc to th e part remain powered; otherwise, jtag signals will not be able to transition the device, even in bypass mode. microsemi recommends that vpump and vjtag pow er supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. vpump programming supply voltage igloo nano devices support single-voltage isp of the configuration flash and flashrom. for programming, vpump should be 3.3 v nominal. duri ng normal device operation, vpump can be left floating or can be tied (pulled up) to any voltage between 0 v and the vpump maximum. programming power supply voltage (vpump) range is listed in the datasheet. when the vpump pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of oscillation from the charge pump circuitry. for proper programming, 0.01 f and 0.33 f capacitors (both rated at 16 v) are to be connected in parallel across vpump and gnd, and positioned as close to the fpga pins as possible. microsemi recommends that vpump and vjtag pow er supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. user pins i/o user input/output the i/o pin functions as an input, output, tristate, or bi directional buffer. input and output signal levels are compatible with the i/o standard selected. during programming, i/os become tristated and weakly pulled up to vcci. with vcci, vmv, and vcc supplies continuously powered up, when the device tr ansitions from programming to operating mode, the i/os are instantly configured to the desired user configuration. unused i/os are configured as follows: ? output buffer is disabled (with tristate value of high impedance) ? input buffer is disabled (with tristate value of high impedance) ? weak pull-up is programmed gl globals gl i/os have access to certain clock conditioning circuitry (and the pll) and/or have direct access to the global network (spines). additionally, the global i/os can be used as regular i/os, since they have identical capabilities. unused gl pins are configured as inputs with pull-up resistors. see more detailed descriptions of global i/o connecti vity in the "clock conditioning circuits in igloo and proasic3 devices" chapter in the igloo nano fpga fabric user?s guide. all inputs labeled gc/gf are direct inputs into the quadrant clocks. for example, if gaa0 is us ed for an input, gaa1 and gaa2 are no longer available for input to the quadr ant globals. all inputs labeled gc/gf are direct inputs into the chip-level globals, and the rest are connec ted to the quadrant globals. the inputs to the global network are multiplexed, and only one input can be used as a global input. refer to the "i/o structures in nano devices" chapter of the igloo nano fpga fabric user?s guide for an explanation of the naming of global pins. ff flash*freeze mode activation pin flash*freeze is available on igloo nano devices. the ff pin is a dedic ated input pin used to enter and exit flash*freeze mode. the ff pin is active low, has the same characteristics as a single-ended i/o, and must meet the maximum rise and fall times. when flash*freeze mode is not used in the design, the ff pin is available as a regular i/o. when flash*freeze mode is used, the ff pin must not be left floating to avoid accidentally entering flash*freeze mode. while in flash*freeze mode, the flash*freeze pin should be constantly asserted. the flash*freeze pin can be used with any single- ended i/o standard supported by the i/o bank in which the pin is located, and input signal levels compatible with the i/o standard selected. the ff pin
igloo nano low power flash fpgas revision 17 3-3 should be treated as a sensitive asynchronous signa l. when defining pin placement and board layout, simultaneously switching outputs (ssos) and their effects on sensitive asynchronous pins must be considered. unused ff or i/o pins are tristated with weak pul l-up. this default config uration applies to both flash*freeze mode and normal operation mo de. no user intervention is required. table 3-1 shows the flash*freeze pin location on the available packages for igloo nano devices. the flash*freeze pin location is independent of device (except for a pq208 package), allowing migration to larger or smaller igloo nano devices while maintainin g the same pin location on the board. refer to the " flash*freeze technology and low power modes" chapter of the igloo nano fpga fabric user?s guide for more information on i/o states during flash*freeze mode. jtag pins low power flash devices have a separate bank for the dedicated jtag pins. the jtag pins can be run at any voltage from 1.5 v to 3.3 v (nominal). vc c must also be powered for the jtag state machine to operate, even if the device is in bypass mode; vjtag alone is insufficient. both vjtag and vcc to the part must be supplied to allow jtag signals to transition the device. isolating the jtag power supply in a separate i/o bank gives greater flexibility in s upply selection and simplifies power supply and pcb design. if the jtag interface is neither used nor planned for use, the vjtag pin together with the trst pin could be tied to gnd. tck test clock test clock input for jtag boundary scan, isp, and ujtag. the tck pin does not have an internal pull-up/-down resistor. if jtag is not used, microsemi recommends tying off tck to gnd through a resistor placed close to the fpga pin. this prevent s jtag operation in case tms enters an undesired state. note that to operate at all vjtag voltages, 500 ? to 1 k ? will satisfy the requirements. refer to table 3-2 for more in formation. table 3-1 ? flash*freeze pin locations for igloo nano devices package flash*freeze pin cs81/uc81 h2 qn48 14 qn68 18 vq100 27 uc36 e2 table 3-2 ? recommended tie-off values for the tck and trst pins vjtag tie-off resistance 1,2 vjtag at 3.3 v 200 ? to 1 k ? vjtag at 2.5 v 200 ? to 1 k ? vjtag at 1.8 v 500 ? to 1 k ? vjtag at 1.5 v 500 ? to 1 k ? notes: 1. the tck pin can be pulled-up or pulled-down. 2. the trst pin is pulled-down. 3. equivalent parallel resistance if more than one device is on the jtag chain
pin descriptions 3-4 revision 17 tdi test data input serial input for jtag boundary scan, isp, and ujtag us age. there is an internal weak pull-up resistor on the tdi pin. tdo test data output serial output for jtag boundary scan, isp, and ujtag usage. tms test mode select the tms pin controls the use of the ieee 1532 boundar y scan pins (tck, tdi, tdo, trst). there is an internal weak pull-up resistor on the tms pin. trst boundary scan reset pin the trst pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan circuitry. there is an internal weak pull-up resistor on the trst pin. if jtag is not used, an external pull-down resistor could be included to ensure the test access port (tap) is held in reset mode. the resistor values must be chosen from ta b l e 3 - 2 and must satisfy the parallel resistance value requirement. the values in ta b l e 3 - 2 correspond to the resistor recommended when a single device is used, and the equivalent parallel resistor when multiple devices are connected via a jtag chain. in critical applications, an upset in the jtag circui t could allow entrance to an undesired jtag state. in such cases, microsemi recommends tying off trst to gnd through a resistor placed close to the fpga pin. note that to operate at all vjtag voltages, 500 ? to 1 k ? will satisfy the requirements. special function pins nc no connect this pin is not connected to circuitry within the devic e. these pins can be driven to any voltage or can be left floating with no effect on the operation of the device. dc do not connect this pin should not be connected to any signals on the pcb. these pins should be left unconnected. packaging semiconductor technology is constantly shrinking in size while growing in capability and functional integration. to enable next-generation silicon tech nologies, semiconductor packages have also evolved to provide improved performance and flexibility. microsemi consistently delivers packages that provide the necessary mechanical and environmental protection to ensure consistent reliability an d performance. microsemi ic packaging technology efficiently supports high-density fpgas with large-pin- count ball grid arrays (bga s), but is also flexible enough to accommodate stringent form factor requi rements for chip scale packaging (csp). in addition, microsemi offers a variety of packages designed to meet your most dema nding application and economic requirements for today's embedded and mobile systems. table 3-3 ? trst and tck pull-down recommendations vjtag tie-off resistance* vjtag at 3.3 v 200 ? to 1 k ? vjtag at 2.5 v 200 ? to 1 k ? vjtag at 1.8 v 500 ? to 1 k ? vjtag at 1.5 v 500 ? to 1 k ? note: equivalent parallel resistance if more than one device is on the jtag chain
igloo nano low power flash fpgas revision 17 3-5 related documents user?s guides igloo nano fpga fabric user?s guide http://www.microsemi.com/soc /documents/igloo_nano_ug.pdf packaging documents the following documents provide packaging information and device selection for low power flash devices. product catalog http://www.microsemi.com/soc /documents/prodcat_pib.pdf lists devices currently recommended for new designs and the packages available for each member of the family. use this document or the datasheet tables to determine the best package for your design, and which package drawing to use. package mechanical drawings http://www.microsemi.com/soc /documents/pckgmechdrwngs.pdf this document contains the package mechanical dr awings for all packages currently or previously supplied by microsemi. use the bookmarks to na vigate to the package mechanical drawings. additional packaging materials are on t he microsemi soc products group website: http://www.microsemi.com/soc/pro ducts/solutions/package/docs.aspx .

revision 17 4-1 4 ? package pin assignments uc36 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx . note: this is the bottom view of the package. 65 4321 a b c d e f pin 1 pad corner
package pin assignments 4-2 revision 17 uc36 pin number agln010 function a1 io21rsb1 a2 io18rsb1 a3 io13rsb1 a4 gdc0/io00rsb0 a5 io06rsb0 a6 gda0/io04rsb0 b1 gec0/io37rsb1 b2 io20rsb1 b3 io15rsb1 b4 io09rsb0 b5 io08rsb0 b6 io07rsb0 c1 io22rsb1 c2 gea0/io34rsb1 c3 gnd c4 gnd c5 vccib0 c6 io02rsb0 d1 io33rsb1 d2 vccib1 d3 vcc d4 vcc d5 io10rsb0 d6 io11rsb0 e1 io32rsb1 e2 ff/io31rsb1 e3 tck e4 vpump e5 trst e6 vjtag f1 io29rsb1 f2 io25rsb1 f3 io23rsb1 f4 tdi f5 tms f6 tdo uc36 pin number agln010 function
igloo nano low power flash fpgas revision 17 4-3 uc81 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx . note: this is the bottom view of the package. 1 2 3 4 5 6 7 8 9 a b c d e f g h j a1 ball pad corner
package pin assignments 4-4 revision 17 uc81 pin number agln020 function a1 io64rsb2 a2 io54rsb2 a3 io57rsb2 a4 io36rsb1 a5 io32rsb1 a6 io24rsb1 a7 io20rsb1 a8 io04rsb0 a9 io08rsb0 b1 io59rsb2 b2 io55rsb2 b3 io62rsb2 b4 io34rsb1 b5 io28rsb1 b6 io22rsb1 b7 io18rsb1 b8 io00rsb0 b9 io03rsb0 c1 io51rsb2 c2 io50rsb2 c3 nc c4 nc c5 nc c6 nc c7 nc c8 io10rsb0 c9 io07rsb0 d1 io49rsb2 d2 io44rsb2 d3 nc d4 vcc d5 vccib2 d6 gnd d7 nc d8 io13rsb0 d9 io12rsb0 e1 gec0/io48rsb2 e2 gea0/io47rsb2 e3 nc e4 vccib1 e5 vcc e6 vccib0 e7 nc e8 gda0/io15rsb0 e9 gdc0/io14rsb0 f1 io46rsb2 f2 io45rsb2 f3 nc f4 gnd f5 vccib1 f6 nc f7 nc f8 io16rsb0 f9 io17rsb0 g1 io43rsb2 g2 io42rsb2 g3 io41rsb2 g4 io31rsb1 g5 nc g6 io21rsb1 g7 nc g8 vjtag g9 trst h1 io40rsb2 h2 ff/io39rsb1 h3 io35rsb1 h4 io29rsb1 h5 io26rsb1 h6 io25rsb1 h7 io19rsb1 h8 tdi h9 tdo uc81 pin number agln020 function j1 io38rsb1 j2 io37rsb1 j3 io33rsb1 j4 io30rsb1 j5 io27rsb1 j6 io23rsb1 j7 tck j8 tms j9 vpump uc81 pin number agln020 function
igloo nano low power flash fpgas revision 17 4-5 uc81 pin number agln030z function a1 io00rsb0 a2 io02rsb0 a3 io06rsb0 a4 io11rsb0 a5 io16rsb0 a6 io19rsb0 a7 io22rsb0 a8 io24rsb0 a9 io26rsb0 b1 io81rsb1 b2 io04rsb0 b3 io10rsb0 b4 io13rsb0 b5 io15rsb0 b6 io20rsb0 b7 io21rsb0 b8 io28rsb0 b9 io25rsb0 c1 io79rsb1 c2 io80rsb1 c3 io08rsb0 c4 io12rsb0 c5 io17rsb0 c6 io14rsb0 c7 io18rsb0 c8 io29rsb0 c9 io27rsb0 d1 io74rsb1 d2 io76rsb1 d3 io77rsb1 d4 vcc d5 vccib0 d6 gnd d7 io23rsb0 d8 io31rsb0 d9 io30rsb0 e1 geb0/io71rsb1 e2 gea0/io72rsb1 e3 gec0/io73rsb1 e4 vccib1 e5 vcc e6 vccib0 e7 gdc0/io32rsb0 e8 gda0/io33rsb0 e9 gdb0/io34rsb0 f1 io68rsb1 f2 io67rsb1 f3 io64rsb1 f4 gnd f5 vccib1 f6 io47rsb1 f7 io36rsb0 f8 io38rsb0 f9 io40rsb0 g1 io65rsb1 g2 io66rsb1 g3 io57rsb1 g4 io53rsb1 g5 io49rsb1 g6 io45rsb1 g7 io46rsb1 g8 vjtag g9 trst h1 io62rsb1 h2 ff/io60rsb1 h3 io58rsb1 h4 io54rsb1 h5 io48rsb1 h6 io43rsb1 h7 io42rsb1 uc81 pin number agln030z function h8 tdi h9 tdo j1 io63rsb1 j2 io61rsb1 j3 io59rsb1 j4 io56rsb1 j5 io52rsb1 j6 io44rsb1 j7 tck j8 tms j9 vpump uc81 pin number agln030z function
package pin assignments 4-6 revision 17 cs81 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx . note: this is the bottom view of the package. 1 2 3 4 5 6 7 8 9 a b c d e f g h j a1 ball pad corner
igloo nano low power flash fpgas revision 17 4-7 cs81 pin number agln020 function a1 io64rsb2 a2 io54rsb2 a3 io57rsb2 a4 io36rsb1 a5 io32rsb1 a6 io24rsb1 a7 io20rsb1 a8 io04rsb0 a9 io08rsb0 b1 io59rsb2 b2 io55rsb2 b3 io62rsb2 b4 io34rsb1 b5 io28rsb1 b6 io22rsb1 b7 io18rsb1 b8 io00rsb0 b9 io03rsb0 c1 io51rsb2 c2 io50rsb2 c3 nc c4 nc c5 nc c6 nc c7 nc c8 io10rsb0 c9 io07rsb0 d1 io49rsb2 d2 io44rsb2 d3 nc d4 vcc d5 vccib2 d6 gnd d7 nc d8 io13rsb0 d9 io12rsb0 e1 gec0/io48rsb2 e2 gea0/io47rsb2 e3 nc e4 vccib1 e5 vcc e6 vccib0 e7 nc e8 gda0/io15rsb0 e9 gdc0/io14rsb0 f1 io46rsb2 f2 io45rsb2 f3 nc f4 gnd f5 vccib1 f6 nc f7 nc f8 io16rsb0 f9 io17rsb0 g1 io43rsb2 g2 io42rsb2 g3 io41rsb2 g4 io31rsb1 g5 nc g6 io21rsb1 g7 nc g8 vjtag g9 trst h1 io40rsb2 h2 ff/io39rsb1 h3 io35rsb1 h4 io29rsb1 h5 io26rsb1 h6 io25rsb1 h7 io19rsb1 h8 tdi h9 tdo cs81 pin number agln020 function j1 io38rsb1 j2 io37rsb1 j3 io33rsb1 j4 io30rsb1 j5 io27rsb1 j6 io23rsb1 j7 tck j8 tms j9 vpump cs81 pin number agln020 function
package pin assignments 4-8 revision 17 cs81 pin number agln030z function a1 io00rsb0 a2 io02rsb0 a3 io06rsb0 a4 io11rsb0 a5 io16rsb0 a6 io19rsb0 a7 io22rsb0 a8 io24rsb0 a9 io26rsb0 b1 io81rsb1 b2 io04rsb0 b3 io10rsb0 b4 io13rsb0 b5 io15rsb0 b6 io20rsb0 b7 io21rsb0 b8 io28rsb0 b9 io25rsb0 c1 io79rsb1 c2 io80rsb1 c3 io08rsb0 c4 io12rsb0 c5 io17rsb0 c6 io14rsb0 c7 io18rsb0 c8 io29rsb0 c9 io27rsb0 d1 io74rsb1 d2 io76rsb1 d3 io77rsb1 d4 vcc d5 vccib0 d6 gnd d7 io23rsb0 d8 io31rsb0 d9 io30rsb0 e1 geb0/io71rsb1 e2 gea0/io72rsb1 e3 gec0/io73rsb1 e4 vccib1 e5 vcc e6 vccib0 e7 gdc0/io32rsb0 e8 gda0/io33rsb0 e9 gdb0/io34rsb0 f1 io68rsb1 f2 io67rsb1 f3 io64rsb1 f4 gnd f5 vccib1 f6 io47rsb1 f7 io36rsb0 f8 io38rsb0 f9 io40rsb0 g1 io65rsb1 g2 io66rsb1 g3 io57rsb1 g4 io53rsb1 g5 io49rsb1 g6 io44rsb1 g7 io46rsb1 g8 vjtag g9 trst h1 io62rsb1 h2 ff/io60rsb1 h3 io58rsb1 h4 io54rsb1 h5 io48rsb1 h6 io43rsb1 h7 io42rsb1 cs81 pin number agln030z function h8 tdi h9 tdo j1 io63rsb1 j2 io61rsb1 j3 io59rsb1 j4 io56rsb1 j5 io52rsb1 j6 io45rsb1 j7 tck j8 tms j9 vpump cs81 pin number agln030z function
igloo nano low power flash fpgas revision 17 4-9 cs81 pin number agln060 function a1 gaa0/io02rsb0 a2 gaa1/io03rsb0 a3 gac0/io06rsb0 a4 io09rsb0 a5 io13rsb0 a6 io18rsb0 a7 gbb0/io21rsb0 a8 gba1/io24rsb0 a9 gba2/io25rsb0 b1 gaa2/io95rsb1 b2 gab0/io04rsb0 b3 gac1/io07rsb0 b4 io08rsb0 b5 io15rsb0 b6 gbc0/io19rsb0 b7 gbb1/io22rsb0 b8 io26rsb0 b9 gbb2/io27rsb0 c1 gab2/io93rsb1 c2 io94rsb1 c3 gnd c4 io10rsb0 c5 io17rsb0 c6 gnd c7 gba0/io23rsb0 c8 gbc2/io29rsb0 c9 io31rsb0 d1 gac2/io91rsb1 d2 io92rsb1 d3 gfa2/io80rsb1 d4 vcc d5 vccib0 d6 gnd d7 gcc2/io43rsb0 d8 gcc1/io35rsb0 d9 gcc0/io36rsb0 e1 gfb0/io83rsb1 e2 gfb1/io84rsb1 e3 gfa1/io81rsb1 e4 vccib1 e5 vcc e6 vccib0 e7 gca1/io39rsb0 e8 gca0/io40rsb0 e9 gcb2/io42rsb0 f1 1 vccplf f2 1 vcomplf f3 gnd f4 gnd f5 vccib1 f6 gnd f7 gda1/io49rsb0 f8 gdc1/io45rsb0 f9 gdc0/io46rsb0 g1 gea0/io69rsb1 g2 gec1/io74rsb1 g3 geb1/io72rsb1 g4 io63rsb1 g5 io60rsb1 g6 io54rsb1 g7 gdb2/io52rsb1 g8 vjtag g9 trst h1 gea1/io70rsb1 h2 ff/geb2/io67rsb1 h3 io65rsb1 h4 io62rsb1 h5 io59rsb1 cs81 pin number agln060 function h6 io56rsb1 h7 2 gda2/io51rsb1 h8 tdi h9 tdo j1 gea2/io68rsb1 j2 gec2/io66rsb1 j3 io64rsb1 j4 io61rsb1 j5 io58rsb1 j6 io55rsb1 j7 tck j8 tms j9 vpump cs81 pin number agln060 function notes: 1. pin numbers f1 and f2 must be connected to ground because a pll is not supported for agln060-cs81. 2. the bus hold attribute (hold previous i/o state in flash* freeze mode) is not supported for pin h7 in agln060-cs81.
package pin assignments 4-10 revision 17 cs81 pin number agln060z function a1 gaa0/io02rsb0 a2 gaa1/io03rsb0 a3 gac0/io06rsb0 a4 io09rsb0 a5 io13rsb0 a6 io18rsb0 a7 gbb0/io21rsb0 a8 gba1/io24rsb0 a9 gba2/io25rsb0 b1 gaa2/io95rsb1 b2 gab0/io04rsb0 b3 gac1/io07rsb0 b4 io08rsb0 b5 io15rsb0 b6 gbc0/io19rsb0 b7 gbb1/io22rsb0 b8 io26rsb0 b9 gbb2/io27rsb0 c1 gab2/io93rsb1 c2 io94rsb1 c3 gnd c4 io10rsb0 c5 io17rsb0 c6 gnd c7 gba0/io23rsb0 c8 gbc2/io29rsb0 c9 io31rsb0 d1 gac2/io91rsb1 d2 io92rsb1 d3 gfa2/io80rsb1 d4 vcc d5 vccib0 d6 gnd d7 gcc2/io43rsb0 d8 gcc1/io35rsb0 d9 gcc0/io36rsb0 e1 gfb0/io83rsb1 e2 gfb1/io84rsb1 e3 gfa1/io81rsb1 e4 vccib1 e5 vcc e6 vccib0 e7 gca1/io39rsb0 e8 gca0/io40rsb0 e9 gcb2/io42rsb0 f1 1 vccplf f2 1 vcomplf f3 gnd f4 gnd f5 vccib1 f6 gnd f7 gda1/io49rsb0 f8 gdc1/io45rsb0 f9 gdc0/io46rsb0 g1 gea0/io69rsb1 g2 gec1/io74rsb1 g3 geb1/io72rsb1 g4 io63rsb1 g5 io60rsb1 g6 io54rsb1 g7 gdb2/io52rsb1 g8 vjtag g9 trst h1 gea1/io70rsb1 h2 ff/geb2/io67rsb1 h3 io65rsb1 h4 io62rsb1 h5 io59rsb1 cs81 pin number agln060z function h6 io56rsb1 h7 2 gda2/io51rsb1 h8 tdi h9 tdo j1 gea2/io68rsb1 j2 gec2/io66rsb1 j3 io64rsb1 j4 io61rsb1 j5 io58rsb1 j6 io55rsb1 j7 tck j8 tms j9 vpump cs81 pin number agln060z function notes: 1. pin numbers f1 and f2 must be connected to groun d because a pll is not supported for agln060z-cs81. 2. the bus hold attribute (hold previous i/o state in flash* freeze mode) is not supporte d for pin h7 in agln060z-cs81.
igloo nano low power flash fpgas revision 17 4-11 cs81 pin number agln125 function a1 gaa0/io00rsb0 a2 gaa1/io01rsb0 a3 gac0/io04rsb0 a4 io13rsb0 a5 io22rsb0 a6 io32rsb0 a7 gbb0/io37rsb0 a8 gba1/io40rsb0 a9 gba2/io41rsb0 b1 gaa2/io132rsb1 b2 gab0/io02rsb0 b3 gac1/io05rsb0 b4 io11rsb0 b5 io25rsb0 b6 gbc0/io35rsb0 b7 gbb1/io38rsb0 b8 io42rsb0 b9 gbb2/io43rsb0 c1 gab2/io130rsb1 c2 io131rsb1 c3 gnd c4 io15rsb0 c5 io28rsb0 c6 gnd c7 gba0/io39rsb0 c8 gbc2/io45rsb0 c9 io47rsb0 d1 gac2/io128rsb1 d2 io129rsb1 d3 gfa2/io117rsb1 d4 vcc d5 vccib0 d6 gnd d7 gcc2/io59rsb0 d8 gcc1/io51rsb0 d9 gcc0/io52rsb0 e1 gfb0/io120rsb1 e2 gfb1/io121rsb1 e3 gfa1/io118rsb1 e4 vccib1 e5 vcc e6 vccib0 e7 gca0/io56rsb0 e8 gca1/io55rsb0 e9 gcb2/io58rsb0 f1* vccplf f2* vcomplf f3 gnd f4 gnd f5 vccib1 f6 gnd f7 gda1/io65rsb0 f8 gdc1/io61rsb0 f9 gdc0/io62rsb0 g1 gea0/io104rsb1 g2 gec0/io108rsb1 g3 geb1/io107rsb1 g4 io96rsb1 g5 io92rsb1 g6 io72rsb1 g7 gdb2/io68rsb1 g8 vjtag g9 trst h1 gea1/io105rsb1 h2 ff/geb2/io102rsb1 h3 io99rsb1 h4 io94rsb1 h5 io91rsb1 h6 io81rsb1 h7 gda2/io67rsb1 h8 tdi h9 tdo cs81 pin number agln125 function j1 gea2/io103rsb1 j2 gec2/io101rsb1 j3 io97rsb1 j4 io93rsb1 j5 io90rsb1 j6 io78rsb1 j7 tck j8 tms j9 vpump cs81 pin number agln125 function note: * pin numbers f1 and f2 must be connected to gr ound because a pll is not supported for agln125-cs81.
package pin assignments 4-12 revision 17 cs8 pin number agln125z function a1 gaa0/io00rsb0 a2 gaa1/io01rsb0 a3 gac0/io04rsb0 a4 io13rsb0 a5 io22rsb0 a6 io32rsb0 a7 gbb0/io37rsb0 a8 gba1/io40rsb0 a9 gba2/io41rsb0 b1 gaa2/io132rsb1 b2 gab0/io02rsb0 b3 gac1/io05rsb0 b4 io11rsb0 b5 io25rsb0 b6 gbc0/io35rsb0 b7 gbb1/io38rsb0 b8 io42rsb0 b9 gbb2/io43rsb0 c1 gab2/io130rsb1 c2 io131rsb1 c3 gnd c4 io15rsb0 c5 io28rsb0 c6 gnd c7 gba0/io39rsb0 c8 gbc2/io45rsb0 c9 io47rsb0 d1 gac2/io128rsb1 d2 io129rsb1 d3 gfa2/io117rsb1 d4 vcc d5 vccib0 d6 gnd d7 gcc2/io59rsb0 d8 gcc1/io51rsb0 d9 gcc0/io52rsb0 e1 gfb0/io120rsb1 e2 gfb1/io121rsb1 e3 gfa1/io118rsb1 e4 vccib1 e5 vcc e6 vccib0 e7 gca0/io56rsb0 e8 gca1/io55rsb0 e9 gcb2/io58rsb0 f1* vccplf f2* vcomplf f3 gnd f4 gnd f5 vccib1 f6 gnd f7 gda1/io65rsb0 f8 gdc1/io61rsb0 f9 gdc0/io62rsb0 g1 gea0/io104rsb1 g2 gec0/io108rsb1 g3 geb1/io107rsb1 g4 io96rsb1 g5 io92rsb1 g6 io72rsb1 g7 gdb2/io68rsb1 g8 vjtag g9 trst h1 gea1/io105rsb1 h2 ff/geb2/io102rsb1 h3 io99rsb1 h4 io94rsb1 h5 io91rsb1 h6 io81rsb1 h7 gda2/io67rsb1 h8 tdi h9 tdo cs8 pin number agln125z function j1 gea2/io103rsb1 j2 gec2/io101rsb1 j3 io97rsb1 j4 io93rsb1 j5 io90rsb1 j6 io78rsb1 j7 tck j8 tms j9 vpump cs8 pin number agln125z function note: * pin numbers f1 and f2 must be connected to gr ound because a pll is not supported for agln125z-cs81.
igloo nano low power flash fpgas revision 17 4-13 cs81 pin number agln250 function a1 gaa0/io00rsb0 a2 gaa1/io01rsb0 a3 gac0/io04rsb0 a4 io13rsb0 a5 io21rsb0 a6 io27rsb0 a7 gbb0/io37rsb0 a8 gba1/io40rsb0 a9 gba2/io41ppb1 b1 gaa2/io118upb3 b2 gab0/io02rsb0 b3 gac1/io05rsb0 b4 io11rsb0 b5 io23rsb0 b6 gbc0/io35rsb0 b7 gbb1/io38rsb0 b8 io41npb1 b9 gbb2/io42psb1 c1 gab2/io117upb3 c2 io118vpb3 c3 gnd c4 io15rsb0 c5 io25rsb0 c6 gnd c7 gba0/io39rsb0 c8 gbc2/io43b1 c9 io43ndb1 d1 gac2/io116usb3 d2 io117vpb3 d3 gfa2/io107psb3 d4 vcc d5 vccib0 d6 gnd d7 io52npb1 d8 gcc1/io48pdb1 d9 gcc0/io48ndb1 e1 gfb0/io109ndb3 e2 gfb1/io109pdb3 e3 gfa1/io108psb3 e4 vccib3 e5 vcc e6 vccib1 e7 gca0/io50ndb1 e8 gca1/io50pdb1 e9 gcb2/io52ppb1 f1* vccplf f2* vcomplf f3 gnd f4 gnd f5 vccib2 f6 gnd f7 gda1/io60usb1 f8 gdc1/io58udb1 f9 gdc0/io58vdb1 g1 gea0/io98ndb3 g2 gec1/io100pdb3 g3 gec0/io100ndb3 g4 io91rsb2 g5 io86rsb2 g6 io71rsb2 g7 gdb2/io62rsb2 g8 vjtag g9 trst h1 gea1/io98pdb3 h2 ff/geb2/io96rsb2 h3 io93rsb2 h4 io90rsb2 h5 io85rsb2 h6 io77rsb2 h7 gda2/io61rsb2 h8 tdi h9 tdo cs81 pin number agln250 function j1 gea2/io97rsb2 j2 gec2/io95rsb2 j3 io92rsb2 j4 io88rsb2 j5 io84rsb2 j6 io74rsb2 j7 tck j8 tms j9 vpump cs81 pin number agln250 function note: * pin numbers f1 and f2 must be connected to gr ound because a pll is not supported for agln250-cs81.
package pin assignments 4-14 revision 17 cs81 pin number agln250z function a1 gaa0/io00rsb0 a2 gaa1/io01rsb0 a3 gac0/io04rsb0 a4 io07rsb0 a5 io09rsb0 a6 io12rsb0 a7 gbb0/io16rsb0 a8 gba1/io19rsb0 a9 gba2/io20rsb1 b1 gaa2/io67rsb3 b2 gab0/io02rsb0 b3 gac1/io05rsb0 b4 io06rsb0 b5 io10rsb0 b6 gbc0/io14rsb0 b7 gbb1/io17rsb0 b8 io21rsb1 b9 gbb2/io22rsb1 c1 gab2/io65rsb3 c2 io66rsb3 c3 gnd c4 io08rsb0 c5 io11rsb0 c6 gnd c7 gba0/io18rsb0 c8 gbc2/io23rsb1 c9 io24rsb1 d1 gac2/io63rsb3 d2 io64rsb3 d3 gfa2/io56rsb3 d4 vcc d5 vccib0 d6 gnd d7 io30rsb1 d8 gcc1/io25rsb1 d9 gcc0/io26rsb1 e1 gfb0/io59rsb3 e2 gfb1/io60rsb3 e3 gfa1/io58rsb3 e4 vccib3 e5 vcc e6 vccib1 e7 gca0/io28rsb1 e8 gca1/io27rsb1 e9 gcb2/io29rsb1 f1* vccplf f2* vcomplf f3 gnd f4 gnd f5 vccib2 f6 gnd f7 gda1/io33rsb1 f8 gdc1/io31rsb1 f9 gdc0/io32rsb1 g1 gea0/io51rsb3 g2 gec1/io54rsb3 g3 gec0/io53rsb3 g4 io45rsb2 g5 io42rsb2 g6 io37rsb2 g7 gdb2/io35rsb2 g8 vjtag g9 trst h1 gea1/io52rsb3 h2 ff/geb2/io49rsb2 h3 io47rsb2 h4 io44rsb2 h5 io41rsb2 h6 io39rsb2 h7 gda2/io34rsb2 h8 tdi h9 tdo cs81 pin number agln250z function j1 gea2/io50rsb2 j2 gec2/io48rsb2 j3 io46rsb2 j4 io43rsb2 j5 io40rsb2 j6 io38rsb2 j7 tck j8 tms j9 vpump cs81 pin number agln250z function note: * pin numbers f1 and f2 must be connected to gr ound because a pll is not supported for agln250z-cs81.
igloo nano low power flash fpgas revision 17 4-15 qn48 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx . notes: 1. this is the bottom view of the package. 2. the die attach paddle of the package is tied to ground (gnd). 48 1 pin 1
package pin assignments 4-16 revision 17 qn48 pin number agln010 function 1 gec0/io37rsb1 2 io36rsb1 3 gea0/io34rsb1 4 io22rsb1 5gnd 6vccib1 7 io24rsb1 8 io33rsb1 9 io26rsb1 10 io32rsb1 11 io27rsb1 12 io29rsb1 13 io30rsb1 14 ff/io31rsb1 15 io28rsb1 16 io25rsb1 17 io23rsb1 18 vcc 19 vccib1 20 io17rsb1 21 io14rsb1 22 tck 23 tdi 24 tms 25 vpump 26 tdo 27 trst 28 vjtag 29 io11rsb0 30 io10rsb0 31 io09rsb0 32 io08rsb0 33 vccib0 34 gnd 35 vcc 36 io07rsb0 37 io06rsb0 38 gda0/io05rsb0 39 io03rsb0 40 gdc0/io01rsb0 41 io12rsb1 42 io13rsb1 43 io15rsb1 44 io16rsb1 45 io18rsb1 46 io19rsb1 47 io20rsb1 48 io21rsb1 qn48 pin number agln010 function
igloo nano low power flash fpgas revision 17 4-17 qn48 pin number agln030z function 1 io82rsb1 2 gec0/io73rsb1 3 gea0/io72rsb1 4 geb0/io71rsb1 5gnd 6 vccib1 7 io68rsb1 8 io67rsb1 9 io66rsb1 10 io65rsb1 11 io64rsb1 12 io62rsb1 13 io61rsb1 14 ff/io60rsb1 15 io57rsb1 16 io55rsb1 17 io53rsb1 18 vcc 19 vccib1 20 io46rsb1 21 io42rsb1 22 tck 23 tdi 24 tms 25 vpump 26 tdo 27 trst 28 vjtag 29 io38rsb0 30 gdb0/io34rsb0 31 gda0/io33rsb0 32 gdc0/io32rsb0 33 vccib0 34 gnd 35 vcc 36 io25rsb0 37 io24rsb0 38 io22rsb0 39 io20rsb0 40 io18rsb0 41 io16rsb0 42 io14rsb0 43 io10rsb0 44 io08rsb0 45 io06rsb0 46 io04rsb0 47 io02rsb0 48 io00rsb0 qn48 pin number agln030z function
package pin assignments 4-18 revision 17 qn68 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx . notes: 1. this is the bottom view of the package. 2. the die attach paddle of the package is tied to ground (gnd). pin a1 mark 1 68
igloo nano low power flash fpgas revision 17 4-19 qn68 pin number agln015 function 1 io60rsb2 2 io54rsb2 3 io52rsb2 4 io50rsb2 5 io49rsb2 6 gec0/io48rsb2 7 gea0/io47rsb2 8vcc 9gnd 10 vccib2 11 io46rsb2 12 io45rsb2 13 io44rsb2 14 io43rsb2 15 io42rsb2 16 io41rsb2 17 io40rsb2 18 ff/io39rsb1 19 io37rsb1 20 io35rsb1 21 io33rsb1 22 io31rsb1 23 io30rsb1 24 vcc 25 gnd 26 vccib1 27 io27rsb1 28 io25rsb1 29 io23rsb1 30 io21rsb1 31 io19rsb1 32 tck 33 tdi 34 tms 35 vpump 36 tdo 37 trst 38 vjtag 39 io17rsb0 40 io16rsb0 41 gda0/io15rsb0 42 gdc0/io14rsb0 43 io13rsb0 44 vccib0 45 gnd 46 vcc 47 io12rsb0 48 io11rsb0 49 io09rsb0 50 io05rsb0 51 io00rsb0 52 io07rsb0 53 io03rsb0 54 io18rsb1 55 io20rsb1 56 io22rsb1 57 io24rsb1 58 io28rsb1 59 nc 60 gnd 61 nc 62 io32rsb1 63 io34rsb1 64 io36rsb1 65 io61rsb2 66 io58rsb2 67 io56rsb2 68 io63rsb2 qn68 pin number agln015 function
package pin assignments 4-20 revision 17 qn68 pin number agln020 function 1 io60rsb2 2 io54rsb2 3 io52rsb2 4 io50rsb2 5 io49rsb2 6 gec0/io48rsb2 7 gea0/io47rsb2 8vcc 9gnd 10 vccib2 11 io46rsb2 12 io45rsb2 13 io44rsb2 14 io43rsb2 15 io42rsb2 16 io41rsb2 17 io40rsb2 18 ff/io39rsb1 19 io37rsb1 20 io35rsb1 21 io33rsb1 22 io31rsb1 23 io30rsb1 24 vcc 25 gnd 26 vccib1 27 io27rsb1 28 io25rsb1 29 io23rsb1 30 io21rsb1 31 io19rsb1 32 tck 33 tdi 34 tms 35 vpump 36 tdo 37 trst 38 vjtag 39 io17rsb0 40 io16rsb0 41 gda0/io15rsb0 42 gdc0/io14rsb0 43 io13rsb0 44 vccib0 45 gnd 46 vcc 47 io12rsb0 48 io11rsb0 49 io09rsb0 50 io05rsb0 51 io00rsb0 52 io07rsb0 53 io03rsb0 54 io18rsb1 55 io20rsb1 56 io22rsb1 57 io24rsb1 58 io28rsb1 59 nc 60 gnd 61 nc 62 io32rsb1 63 io34rsb1 64 io36rsb1 65 io61rsb2 66 io58rsb2 67 io56rsb2 68 io63rsb2 qn68 pin number agln020 function
igloo nano low power flash fpgas revision 17 4-21 qn68 pin number agln030z function 1 io82rsb1 2 io80rsb1 3 io78rsb1 4 io76rsb1 5 gec0/io73rsb1 6 gea0/io72rsb1 7 geb0/io71rsb1 8vcc 9gnd 10 vccib1 11 io68rsb1 12 io67rsb1 13 io66rsb1 14 io65rsb1 15 io64rsb1 16 io63rsb1 17 io62rsb1 18 ff/io60rsb1 19 io58rsb1 20 io56rsb1 21 io54rsb1 22 io52rsb1 23 io51rsb1 24 vcc 25 gnd 26 vccib1 27 io50rsb1 28 io48rsb1 29 io46rsb1 30 io44rsb1 31 io42rsb1 32 tck 33 tdi 34 tms 35 vpump 36 tdo 37 trst 38 vjtag 39 io40rsb0 40 io37rsb0 41 gdb0/io34rsb0 42 gda0/io33rsb0 43 gdc0/io32rsb0 44 vccib0 45 gnd 46 vcc 47 io31rsb0 48 io29rsb0 49 io28rsb0 50 io27rsb0 51 io25rsb0 52 io24rsb0 53 io22rsb0 54 io21rsb0 55 io19rsb0 56 io17rsb0 57 io15rsb0 58 io14rsb0 59 vccib0 60 gnd 61 vcc 62 io12rsb0 63 io10rsb0 64 io08rsb0 65 io06rsb0 66 io04rsb0 67 io02rsb0 68 io00rsb0 qn68 pin number agln030z function
package pin assignments 4-22 revision 17 vq100 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx . note: this is the top view of the package. 1 100
igloo nano low power flash fpgas revision 17 4-23 vq100 pin number agln030z function 1gnd 2 io82rsb1 3 io81rsb1 4 io80rsb1 5 io79rsb1 6 io78rsb1 7 io77rsb1 8 io76rsb1 9gnd 10 io75rsb1 11 io74rsb1 12 gec0/io73rsb1 13 gea0/io72rsb1 14 geb0/io71rsb1 15 io70rsb1 16 io69rsb1 17 vcc 18 vccib1 19 io68rsb1 20 io67rsb1 21 io66rsb1 22 io65rsb1 23 io64rsb1 24 io63rsb1 25 io62rsb1 26 io61rsb1 27 ff/io60rsb1 28 io59rsb1 29 io58rsb1 30 io57rsb1 31 io56rsb1 32 io55rsb1 33 io54rsb1 34 io53rsb1 35 io52rsb1 36 io51rsb1 37 vcc 38 gnd 39 vccib1 40 io49rsb1 41 io47rsb1 42 io46rsb1 43 io45rsb1 44 io44rsb1 45 io43rsb1 46 io42rsb1 47 tck 48 tdi 49 tms 50 nc 51 gnd 52 vpump 53 nc 54 tdo 55 trst 56 vjtag 57 io41rsb0 58 io40rsb0 59 io39rsb0 60 io38rsb0 61 io37rsb0 62 io36rsb0 63 gdb0/io34rsb0 64 gda0/io33rsb0 65 gdc0/io32rsb0 66 vccib0 67 gnd 68 vcc 69 io31rsb0 70 io30rsb0 vq100 pin number agln030z function 71 io29rsb0 72 io28rsb0 73 io27rsb0 74 io26rsb0 75 io25rsb0 76 io24rsb0 77 io23rsb0 78 io22rsb0 79 io21rsb0 80 io20rsb0 81 io19rsb0 82 io18rsb0 83 io17rsb0 84 io16rsb0 85 io15rsb0 86 io14rsb0 87 vccib0 88 gnd 89 vcc 90 io12rsb0 91 io10rsb0 92 io08rsb0 93 io07rsb0 94 io06rsb0 95 io05rsb0 96 io04rsb0 97 io03rsb0 98 io02rsb0 99 io01rsb0 100 io00rsb0 vq100 pin number agln030z function
package pin assignments 4-24 revision 17 vq100 pin number agln060 function 1gnd 2 gaa2/io51rsb1 3 io52rsb1 4 gab2/io53rsb1 5 io95rsb1 6 gac2/io94rsb1 7 io93rsb1 8 io92rsb1 9gnd 10 gfb1/io87rsb1 11 gfb0/io86rsb1 12 vcomplf 13 gfa0/io85rsb1 14 vccplf 15 gfa1/io84rsb1 16 gfa2/io83rsb1 17 vcc 18 vccib1 19 gec1/io77rsb1 20 geb1/io75rsb1 21 geb0/io74rsb1 22 gea1/io73rsb1 23 gea0/io72rsb1 24 vmv1 25 gndq 26 gea2/io71rsb1 27 ff/geb2/io70rsb1 28 gec2/io69rsb1 29 io68rsb1 30 io67rsb1 31 io66rsb1 32 io65rsb1 33 io64rsb1 34 io63rsb1 35 io62rsb1 36 io61rsb1 37 vcc 38 gnd 39 vccib1 40 io60rsb1 41 io59rsb1 42 io58rsb1 43 io57rsb1 44 gdc2/io56rsb1 45* gdb2/io55rsb1 46 gda2/io54rsb1 47 tck 48 tdi 49 tms 50 vmv1 51 gnd 52 vpump 53 nc 54 tdo 55 trst 56 vjtag 57 gda1/io49rsb0 58 gdc0/io46rsb0 59 gdc1/io45rsb0 60 gcc2/io43rsb0 61 gcb2/io42rsb0 62 gca0/io40rsb0 63 gca1/io39rsb0 64 gcc0/io36rsb0 65 gcc1/io35rsb0 66 vccib0 67 gnd 68 vcc 69 io31rsb0 70 gbc2/io29rsb0 vq100 pin number agln060 function 71 gbb2/io27rsb0 72 io26rsb0 73 gba2/io25rsb0 74 vmv0 75 gndq 76 gba1/io24rsb0 77 gba0/io23rsb0 78 gbb1/io22rsb0 79 gbb0/io21rsb0 80 gbc1/io20rsb0 81 gbc0/io19rsb0 82 io18rsb0 83 io17rsb0 84 io15rsb0 85 io13rsb0 86 io11rsb0 87 vccib0 88 gnd 89 vcc 90 io10rsb0 91 io09rsb0 92 io08rsb0 93 gac1/io07rsb0 94 gac0/io06rsb0 95 gab1/io05rsb0 96 gab0/io04rsb0 97 gaa1/io03rsb0 98 gaa0/io02rsb0 99 io01rsb0 100 io00rsb0 vq100 pin number agln060 function note: *the bus hold attribute (hold previous i/o state in flas h*freeze mode) is not support ed for pin 45 in agln060- vq100.
igloo nano low power flash fpgas revision 17 4-25 vq100 pin number agln060z function 1gnd 2 gaa2/io51rsb1 3 io52rsb1 4 gab2/io53rsb1 5 io95rsb1 6 gac2/io94rsb1 7 io93rsb1 8 io92rsb1 9gnd 10 gfb1/io87rsb1 11 gfb0/io86rsb1 12 vcomplf 13 gfa0/io85rsb1 14 vccplf 15 gfa1/io84rsb1 16 gfa2/io83rsb1 17 vcc 18 vccib1 19 gec1/io77rsb1 20 geb1/io75rsb1 21 geb0/io74rsb1 22 gea1/io73rsb1 23 gea0/io72rsb1 24 vmv1 25 gndq 26 gea2/io71rsb1 27 ff/geb2/io70rsb1 28 gec2/io69rsb1 29 io68rsb1 30 io67rsb1 31 io66rsb1 32 io65rsb1 33 io64rsb1 34 io63rsb1 35 io62rsb1 36 io61rsb1 37 vcc 38 gnd 39 vccib1 40 io60rsb1 41 io59rsb1 42 io58rsb1 43 io57rsb1 44 gdc2/io56rsb1 45* gdb2/io55rsb1 46 gda2/io54rsb1 47 tck 48 tdi 49 tms 50 vmv1 51 gnd 52 vpump 53 nc 54 tdo 55 trst 56 vjtag 57 gda1/io49rsb0 58 gdc0/io46rsb0 59 gdc1/io45rsb0 60 gcc2/io43rsb0 61 gcb2/io42rsb0 62 gca0/io40rsb0 63 gca1/io39rsb0 64 gcc0/io36rsb0 65 gcc1/io35rsb0 66 vccib0 67 gnd 68 vcc vq100 pin number agln060z function 69 io31rsb0 70 gbc2/io29rsb0 71 gbb2/io27rsb0 72 io26rsb0 73 gba2/io25rsb0 74 vmv0 75 gndq 76 gba1/io24rsb0 77 gba0/io23rsb0 78 gbb1/io22rsb0 79 gbb0/io21rsb0 80 gbc1/io20rsb0 81 gbc0/io19rsb0 82 io18rsb0 83 io17rsb0 84 io15rsb0 85 io13rsb0 86 io11rsb0 87 vccib0 88 gnd 89 vcc 90 io10rsb0 91 io09rsb0 92 io08rsb0 93 gac1/io07rsb0 94 gac0/io06rsb0 95 gab1/io05rsb0 96 gab0/io04rsb0 97 gaa1/io03rsb0 98 gaa0/io02rsb0 99 io01rsb0 100 io00rsb0 vq100 pin number agln060z function note: *the bus hold attribute (hold previous i/o state in flas h*freeze mode) is not support ed for pin 45 in agln060z- vq100.
package pin assignments 4-26 revision 17 vq100 pin number agln125 function 1gnd 2 gaa2/io67rsb1 3 io68rsb1 4 gab2/io69rsb1 5 io132rsb1 6 gac2/io131rsb1 7 io130rsb1 8 io129rsb1 9gnd 10 gfb1/io124rsb1 11 gfb0/io123rsb1 12 vcomplf 13 gfa0/io122rsb1 14 vccplf 15 gfa1/io121rsb1 16 gfa2/io120rsb1 17 vcc 18 vccib1 19 gec0/io111rsb1 20 geb1/io110rsb1 21 geb0/io109rsb1 22 gea1/io108rsb1 23 gea0/io107rsb1 24 vmv1 25 gndq 26 gea2/io106rsb1 27 ff/geb2/io105rsb1 28 gec2/io104rsb1 29 io102rsb1 30 io100rsb1 31 io99rsb1 32 io97rsb1 33 io96rsb1 34 io95rsb1 35 io94rsb1 36 io93rsb1 37 vcc 38 gnd 39 vccib1 40 io87rsb1 41 io84rsb1 42 io81rsb1 43 io75rsb1 44 gdc2/io72rsb1 45 gdb2/io71rsb1 46 gda2/io70rsb1 47 tck 48 tdi 49 tms 50 vmv1 51 gnd 52 vpump 53 nc 54 tdo 55 trst 56 vjtag 57 gda1/io65rsb0 58 gdc0/io62rsb0 59 gdc1/io61rsb0 60 gcc2/io59rsb0 61 gcb2/io58rsb0 62 gca0/io56rsb0 63 gca1/io55rsb0 64 gcc0/io52rsb0 65 gcc1/io51rsb0 66 vccib0 67 gnd 68 vcc 69 io47rsb0 70 gbc2/io45rsb0 71 gbb2/io43rsb0 72 io42rsb0 vq100 pin number agln125 function 73 gba2/io41rsb0 74 vmv0 75 gndq 76 gba1/io40rsb0 77 gba0/io39rsb0 78 gbb1/io38rsb0 79 gbb0/io37rsb0 80 gbc1/io36rsb0 81 gbc0/io35rsb0 82 io32rsb0 83 io28rsb0 84 io25rsb0 85 io22rsb0 86 io19rsb0 87 vccib0 88 gnd 89 vcc 90 io15rsb0 91 io13rsb0 92 io11rsb0 93 io09rsb0 94 io07rsb0 95 gac1/io05rsb0 96 gac0/io04rsb0 97 gab1/io03rsb0 98 gab0/io02rsb0 99 gaa1/io01rsb0 100 gaa0/io00rsb0 vq100 pin number agln125 function
igloo nano low power flash fpgas revision 17 4-27 vq100 pin number agln125z function 1gnd 2 gaa2/io67rsb1 3 io68rsb1 4 gab2/io69rsb1 5 io132rsb1 6 gac2/io131rsb1 7 io130rsb1 8 io129rsb1 9gnd 10 gfb1/io124rsb1 11 gfb0/io123rsb1 12 vcomplf 13 gfa0/io122rsb1 14 vccplf 15 gfa1/io121rsb1 16 gfa2/io120rsb1 17 vcc 18 vccib1 19 gec0/io111rsb1 20 geb1/io110rsb1 21 geb0/io109rsb1 22 gea1/io108rsb1 23 gea0/io107rsb1 24 vmv1 25 gndq 26 gea2/io106rsb1 27 ff/geb2/io105rsb1 28 gec2/io104rsb1 29 io102rsb1 30 io100rsb1 31 io99rsb1 32 io97rsb1 33 io96rsb1 34 io95rsb1 35 io94rsb1 36 io93rsb1 37 vcc 38 gnd 39 vccib1 40 io87rsb1 41 io84rsb1 42 io81rsb1 43 io75rsb1 44 gdc2/io72rsb1 45 gdb2/io71rsb1 46 gda2/io70rsb1 47 tck 48 tdi 49 tms 50 vmv1 51 gnd 52 vpump 53 nc 54 tdo 55 trst 56 vjtag 57 gda1/io65rsb0 58 gdc0/io62rsb0 59 gdc1/io61rsb0 60 gcc2/io59rsb0 61 gcb2/io58rsb0 62 gca0/io56rsb0 63 gca1/io55rsb0 64 gcc0/io52rsb0 65 gcc1/io51rsb0 66 vccib0 67 gnd 68 vcc 69 io47rsb0 70 gbc2/io45rsb0 vq100 pin number agln125z function 71 gbb2/io43rsb0 72 io42rsb0 73 gba2/io41rsb0 74 vmv0 75 gndq 76 gba1/io40rsb0 77 gba0/io39rsb0 78 gbb1/io38rsb0 79 gbb0/io37rsb0 80 gbc1/io36rsb0 81 gbc0/io35rsb0 82 io32rsb0 83 io28rsb0 84 io25rsb0 85 io22rsb0 86 io19rsb0 87 vccib0 88 gnd 89 vcc 90 io15rsb0 91 io13rsb0 92 io11rsb0 93 io09rsb0 94 io07rsb0 95 gac1/io05rsb0 96 gac0/io04rsb0 97 gab1/io03rsb0 98 gab0/io02rsb0 99 gaa1/io01rsb0 100 gaa0/io00rsb0 vq100 pin number agln125z function
package pin assignments 4-28 revision 17 vq100 pin number agln250 function 1gnd 2 gaa2/io67rsb3 3 io66rsb3 4 gab2/io65rsb3 5 io64rsb3 6 gac2/io63rsb3 7 io62rsb3 8 io61rsb3 9gnd 10 gfb1/io60rsb3 11 gfb0/io59rsb3 12 vcomplf 13 gfa0/io57rsb3 14 vccplf 15 gfa1/io58rsb3 16 gfa2/io56rsb3 17 vcc 18 vccib3 19 gfc2/io55rsb3 20 gec1/io54rsb3 21 gec0/io53rsb3 22 gea1/io52rsb3 23 gea0/io51rsb3 24 vmv3 25 gndq 26 gea2/io50rsb2 27 ff/geb2/io49rsb2 28 gec2/io48rsb2 29 io47rsb2 30 io46rsb2 31 io45rsb2 32 io44rsb2 33 io43rsb2 34 io42rsb2 35 io41rsb2 36 io40rsb2 37 vcc 38 gnd 39 vccib2 40 io39rsb2 41 io38rsb2 42 io37rsb2 43 gdc2/io36rsb2 44 gdb2/io35rsb2 45 gda2/io34rsb2 46 gndq 47 tck 48 tdi 49 tms 50 vmv2 51 gnd 52 vpump 53 nc 54 tdo 55 trst 56 vjtag 57 gda1/io33rsb1 58 gdc0/io32rsb1 59 gdc1/io31rsb1 60 io30rsb1 61 gcb2/io29rsb1 62 gca1/io27rsb1 63 gca0/io28rsb1 64 gcc0/io26rsb1 65 gcc1/io25rsb1 66 vccib1 67 gnd 68 vcc 69 io24rsb1 70 gbc2/io23rsb1 71 gbb2/io22rsb1 72 io21rsb1 vq100 pin number agln250 function 73 gba2/io20rsb1 74 vmv1 75 gndq 76 gba1/io19rsb0 77 gba0/io18rsb0 78 gbb1/io17rsb0 79 gbb0/io16rsb0 80 gbc1/io15rsb0 81 gbc0/io14rsb0 82 io13rsb0 83 io12rsb0 84 io11rsb0 85 io10rsb0 86 io09rsb0 87 vccib0 88 gnd 89 vcc 90 io08rsb0 91 io07rsb0 92 io06rsb0 93 gac1/io05rsb0 94 gac0/io04rsb0 95 gab1/io03rsb0 96 gab0/io02rsb0 97 gaa1/io01rsb0 98 gaa0/io00rsb0 99 gndq 100 vmv0 vq100 pin number agln250 function
igloo nano low power flash fpgas revision 17 4-29 vq100 pin number agln250z function 1gnd 2 gaa2/io67rsb3 3 io66rsb3 4 gab2/io65rsb3 5 io64rsb3 6 gac2/io63rsb3 7 io62rsb3 8 io61rsb3 9gnd 10 gfb1/io60rsb3 11 gfb0/io59rsb3 12 vcomplf 13 gfa0/io57rsb3 14 vccplf 15 gfa1/io58rsb3 16 gfa2/io56rsb3 17 vcc 18 vccib3 19 gfc2/io55rsb3 20 gec1/io54rsb3 21 gec0/io53rsb3 22 gea1/io52rsb3 23 gea0/io51rsb3 24 vmv3 25 gndq 26 gea2/io50rsb2 27 ff/geb2/io49rsb2 28 gec2/io48rsb2 29 io47rsb2 30 io46rsb2 31 io45rsb2 32 io44rsb2 33 io43rsb2 34 io42rsb2 35 io41rsb2 36 io40rsb2 37 vcc 38 gnd 39 vccib2 40 io39rsb2 41 io38rsb2 42 io37rsb2 43 gdc2/io36rsb2 44 gdb2/io35rsb2 45 gda2/io34rsb2 46 gndq 47 tck 48 tdi 49 tms 50 vmv2 51 gnd 52 vpump 53 nc 54 tdo 55 trst 56 vjtag 57 gda1/io33rsb1 58 gdc0/io32rsb1 59 gdc1/io31rsb1 60 io30rsb1 61 gcb2/io29rsb1 62 gca1/io27rsb1 63 gca0/io28rsb1 64 gcc0/io26rsb1 65 gcc1/io25rsb1 66 vccib1 67 gnd 68 vcc 69 io24rsb1 70 gbc2/io23rsb1 71 gbb2/io22rsb1 72 io21rsb1 vq100 pin number agln250z function 73 gba2/io20rsb1 74 vmv1 75 gndq 76 gba1/io19rsb0 77 gba0/io18rsb0 78 gbb1/io17rsb0 79 gbb0/io16rsb0 80 gbc1/io15rsb0 81 gbc0/io14rsb0 82 io13rsb0 83 io12rsb0 84 io11rsb0 85 io10rsb0 86 io09rsb0 87 vccib0 88 gnd 89 vcc 90 io08rsb0 91 io07rsb0 92 io06rsb0 93 gac1/io05rsb0 94 gac0/io04rsb0 95 gab1/io03rsb0 96 gab0/io02rsb0 97 gaa1/io01rsb0 98 gaa0/io00rsb0 99 gndq 100 vmv0 vq100 pin number agln250z function

revision 17 5-1 5 ? datasheet information list of changes the following table lists critical changes that were made in each version of the igloo nano datasheet. revision changes page revision 17 (may 2013) deleted details related to ambient temperature from "enhanced commercial temperature range" , "igloo nano ordering information" , "temperature grade offerings" , and table 2-2 ? recommended operating conditions 1 to remove ambiguities arising due to the same, and modified note 2 (sar 47063). i , iii , iv , and 2-2 revision 16 (december 2012) the "igloo nano ordering information" section has been updated to mention "y" as "blank" mentioning "device does not includ e license to implement ip based on the cryptography research, inc. (cri ) patent portfolio" (sar 43174). iii the note in table 2-100 ? igloo nano ccc/pll specification and table 2-101 ? igloo nano ccc/pll specification referring the reader to smartgen was revised to refer instead to the online help associated with the core (sar 42565). 2-70 , 2-71 live at power-up (lapu) has been replaced with ?instant on?. na revision 15 (september 2012) the status of the agln125 device has been mo dified from ?advance? to ?production? in the "igloo nano device status" section (sar 41416). ii libero integrated design environment (ide) was changed to libero system-on-chip (soc) throughout the document (sar 40274). na revision 14 (september 2012) the "security" section was modified to clarify that microsemi does not support read-back of programmed data. 1-2 revision 13 (june 2012) figure figure 2-34 ? fifo read and figure 2-35 ? fifo write have been added (sar 34842). 2-82 the following sentence was removed from the "vmvx i/o supply voltage (quiet)" section in the "pin descriptions" section : "within the package, the vmv plane is decoupled from the simultaneous switching noise originating from the output buffer vcci domain" and replaced with ?within the package, the vmv plane biases the input stage of the i/os in the i/o banks? (sar 38319). the datasheet me ntions that "vmv pins must be connected to the corresponding vcci pins" for an esd enhancement. 3-1 revision 12 (march 2012) the "in-system programming (isp) and security" section and "security" section were revised to clarify that although no existing security measures can give an absolute guarantee, microsemi fpgas impl ement the best security available in the industry (sar 34663). i , 1-2 notes indicating that agln015 is not recommended for new designs have been added (sar 35759). notes indicating that nano-z devices are not recommended for new designs have been added. the "devices not recommended for new designs" section is new (sar 36759). ii , iii the y security option and licensed dpa logo were added to the "igloo nano ordering information" section . the trademarked licensed dpa logo identifies that a product is covered by a dpa counter-measures license from cryptography research (sar 34722). iii the following sentence was removed from the "advanced architecture" section : "in addition, extensive on-chip programming circ uitry enables rapid, single-voltage (3.3 v) programming of igloo nano devices via an ieee 1532 jtag interface" (sar 34683). 1-3
datasheet information 5-2 revision 17 revision 12 (continued) the "specifying i/o states du ring programming" section is new (sar 34694). 1-9 the reference to guidelines for global spines and versatile rows, given in the "global clock contribution?p clock " section , was corrected to t he "spine architecture" section of the global resources chapter in the igloo nano fpga fabric user's guide (sar 34732). 2-12 figure 2-4 has been modified for din waveform; the rise and fall time label has been changed to tdin (37106). 2-16 the ac loading figures in the "single-ended i/o characteristics" section were updated to match tables in the "summary of i/o timing characteristics ? default i/o software settings" section (sar 34885). 2-26 , 2-20 the notes regarding drive strength in the "summary of i/o timing characteristics ? default i/o software settings" section , "3.3 v lvcmos wide range" section and "1.2 v lvcmos wide range" section tables were revised for clarification. they now state that the minimum drive strength for the default so ftware configuration when run in wide range is 100 a. the drive strength displayed in so ftware is supported in normal range only. for a detailed i/v curve, refer to the ibis models (sar 34765). 2-20 , 2-29 , 2-40 added values for minimum pulse width and removed the frmax row from ta b l e 2 - 8 8 through ta b l e 2 - 9 9 in the "global tree timing ch aracteristics" section . use the software to determine the frmax for the device you are using (sar 36953). 2-64 to 2-69 table 2-100 ? igloo nano ccc/pll specification and table 2-101 ? igloo nano ccc/pll specification were updated. a note was added indicating that when the ccc/pll core is generated by mircosemi core generator software, not all delay values of the specified delay increments are available (sar 34817). 2-70 and 2-71 the port names in the sram "timing waveforms" , sram "timing characteristics" tables, figure 2-36 ? fifo reset , and the fifo "timing characteristics" tables were revised to ensure consistency with the software names (sar 35754). reference was made to a new application note, simultaneous read-write operations in dual-port sram for flash-based csocs and fpga s , which covers these cases in detail (sar 34865). 2-74 , 2-77 , 2-85 the "pin descriptions" chapter has been added (sar 34770). 3-1 package names used in the "package pin assignments" section were revised to match standards given in package mechanical drawings (sar 34770). 4-1 revision 11 (jul 2010) the status of the agln060 device has changed from advance to production. ii the values for pac1, pac2, pac3, and pac4 were updated in table 2-15 ? different components contributing to dynamic power consumption in igloo nano devices for 1.5 v core supply voltage (sar 26404). 2-10 the values for pac1, pac2, pac3, and pac4 were updated in table 2-17 ? different components contributing to dynamic power consumption in igloo nano devices for 1.2 v core supply voltage (sar 26404). 2-11 july 2010 the versioning system for datasheet s has been changed. datasheets are assigned a revision number that increments each time the datasheet is revised. the "igloo nano device status" table on page ii indicates the status for each device in the device family. n/a revision changes page
igloo nano low power flash fpgas revision 17 5-3 revision 10 (apr 2010) references to differential inputs were re moved from the datasheet, since igloo nano devices do not support differential inputs (sar 21449). n/a a parenthetical note, "hold previous i/o stat e in flash*freeze mode," was added to each occurrence of bus hold in the datasheet (sar 24079). n/a the "in-system programming (i sp) and security" section was revised to add 1.2 v programming. i the note connec ted with the "igloo nano ordering information" table was revised to clarify features not available for z feature grade devices. iii the "igloo nano device status" table is new. ii the definition of c in the "temperature grade offerings" table was changed to "extended commercial temperature range." iv 1.2 v wide range was added to the list of voltage ranges in the "i/os with advanced i/o standards" section . 1-8 a note was added to table 2-2 ? recommended operating conditions 1 regarding switching from 1.2 v to 1.5 v core volt age for in-system pr ogramming. the vjtag voltage was changed from "1.425 to 3.6" to "1.4 to 3.6" (sar 24052). the note regarding voltage for programming v2 and v5 devices was revised (sar 25213). the maximum value for vpump programming voltage (operation mode) was changed from 3.45 v to 3.6 v (sar 25220). 2-2 table 2-6 ? temperature and voltage derati ng factors for timing delays (normalized to tj = 70c, vcc = 1.425 v) and table 2-7 ? temperature and voltage derating factors for timing delays (normalized to tj = 70c, vcc = 1.14 v) were updated. table 2-8 ? power supply state per mode is new. 2-6 , 2-7 the tables in the "quiescent supply current" section were updated (sar 24882 and sar 24112). 2-7 vjtag was removed from table 2-10 ? quiescent supply current (idd) characteristics, igloo nano sleep mode* (sars 24112, 24882, and 79503). 2-8 the note stating what was included in i dd was removed from table 2-11 ? quiescent supply current (idd) characteristics, igloo nano shutdown mode . the note, "per vcci or vjtag bank" was removed from table 2-12 ? quiescent supply current (idd), no igloo nano flash*freeze mode 1 . the note giving i dd was changed to "i dd = n banks * i cci + i cca ." 2-8 the values in table 2-13 ? summary of i/o input buffer power (per pin) ? default i/o software settings and table 2-14 ? summary of i/o output buffer power (per pin) ? default i/o software settings 1 were updated. wide range support information was added. 2-9 revision changes page
datasheet information 5-4 revision 17 revision 10 (continued) the following tables were updated with current available information. the equivalent software default drive strength option was added. table 2-21 ? summary of maximum and minimum dc input and output levels table 2-25 ? summary of i/o timing characteristics?software default settings table 2-26 ? summary of i/o timing characteristics?software default settings table 2-28 ? i/o output buffer maximum resistances 1 table 2-29 ? i/o weak pull-up/pull-down resistances table 2-30 ? i/o short currents iosh/iosl timing tables in the "single-ended i/o characteristics" section , including new tables for 3.3 v and 1.2 v lvcmos wide range. table 2-40 ? minimum and maximum dc input and output levels for lvcmos 3.3 v wide range table 2-63 ? minimum and maximum dc input and output levels table 2-67 ? minimum and maximum dc input and output levels (new) 2-19 through 2-40 the formulas in the notes to table 2-29 ? i/o weak pull-up/pull-down resistances were revised (sar 21348). 2-24 the text introducing table 2-31 ? duration of short circuit event before failure was revised to state six months at 100 instead of three months at 110 for reliability concerns. the row for 110 was removed from the table. 2-25 the following sentence was deleted from the "2.5 v lvcmos" section (sar 24916): "it uses a 5-v tolerant input buffer and push-pull output buffer." 2-32 the f ddrimax and f ddomax values were added to tables in the "ddr module specifications" section (sar 23919). a note was added stating that ddr is not supported for agln010, agln015, and agln020. 2-51 tables in the "global tree timing characteristics" section were updated with new information available. 2-64 table 2-100 ? igloo nano ccc/pll specification and table 2-101 ? igloo nano ccc/pll specification were revised (sar 79390). 2-70 , 2-71 tables in the sram "timing characteristics" section and fifo "timing characteristics" section were updated with new information available. 2-77 , 2-85 table 3-3 ? trst and tck pull-down recommendations is new. 3-4 a note was added to the "cs81" pin tables for agln060, agln060z, agln125, agln125z, agln250, and agln250z indicating that pins f1 and f2 must be grounded (sar 25007). 4-9 , through 4-14 a note was added to the "cs81" and "vq100" pin tables for agln060 and agln060z stating that bus hold is not available for pin h7 or pin 45 (sar 24079). 4-9 , 4-24 the agln250 function for pin c8 in the "cs81" table was revised (sar 22134). 4-13 revision changes page
igloo nano low power flash fpgas revision 17 5-5 revision / version changes page revision 9 (mar2010) product brief advance v0.9 packaging advance v0.8 all product tables and pin tables were updated to show clearly that agln030 is available only in the z f eature grade at this time. the nano-z feature grade devices are designated with a z at the end of the part number. n/a revision 8 (jan 2009) the "reprogrammable flash technology" section was revised to add "250 mhz (1.5 v systems) and 160 mhz (1.2 v systems) system performance." i product brief advance v0.8 the note for agln030 in the "igloo nano devices" table and "i/os per package" table was revised to remove the statement regarding package compatibility with lower density nano devices. ii , ii the "i/os with advanced i/o standards" section was revised to add definitions for hot-swap and cold-sparing. 1-8 packaging advance v0.7 the "uc81" , "cs81" , "qn48" , and "qn68" pin tables for agln030 are new. 4-5 , 4-8 , 4-17 , 4-21 the "cs81" pin table for agln060 is new. 4-9 the "cs81" and "vq100" pin tables for agln060z are new. 4-10 , 4-25 the "cs8" and "vq100" pin tables for agln125z are new. 4-12 , 4-27 the "cs81" and "vq100" pin tables for agln250z is new. 4-14 , 4-29 revision 7 (apr 2009) product brief advance v0.7 dc and switching characteristics advance v0.3 the ?f speed grade is no longer of fered for igloo nano devices and was removed from the datasheet. n/a revision 6 (mar 2009) packaging advance v0.6 the "vq100" pin table for agln030 is new. 4-23 revision 5 (feb 2009) packaging advance v0.5 the "100-pin qfn" section was removed. n/a revision 4 (feb 2009) the qn100 package was remo ved for all devices. n/a product brief advance v0.6 "igloo nano devices" table was updated to change the maximum user i/os for agln030 from 81 to 77. ii the "device marking" section is new. iii revision 3 (feb 2009) product brief advance v0.5 the following table note was removed from "igloo nano devices" table : "six chip (main) and three quadrant global networks are available for agln060 and above." ii the cs81 package was added for agln250 in the "igloo nano products available in the z feature grade" table. iv packaging advance v0.4 the "uc81" and "cs81" pin tables for agln020 are new. 4-4 , 4-7 the "cs81" pin table for agln250 is new. 4-13
datasheet information 5-6 revision 17 revision 2 (dec 2008) product brief advance v0.4 the second table note in "igloo nano devices" table was revised to state, "agln060, agln125, and agln250 in th e cs81 package do not support plls. agln030 and smaller devices do not support this feature ." ii the i/os per package for cs81 were revised to 60 for agln060, agln125, and agln250 in the "i/os per package" table. ii packaging advance v0.3 the "uc36" pin table is new. 4-2 revision 1 (nov 2008) product brief advance v0.3 the "advanced i/os" section was updated to include wide power supply voltage support for 1.14 v to 1.575 v. i the agln030 device was added to product tables and replaces agl030 entries that were formerly in the tables. iv the "i/os per package" table was updated for the cs81 package to change the number of i/os for agln060, agln 125, and agln250 from 66 to 64. ii the "wide range i/o support" section is new. 1-8 the table notes and references were revised in table 2-2 ? recommended operating conditions 1 . vmv was included with vcci and a table note was added stating, "vmv pins must be connecte d to the corresponding vcci pins. see pin descriptions for further info rmation." please review carefully. 2-2 vjtag was added to the list in the table note for table 2-9 ? quiescent supply current (idd) characteristics, igloo nano flash*freeze mode* . values were added for agln010, agln015, and agln030 for 1.5 v. 2-7 vcci was removed from the list in the table note for table 2-10 ? quiescent supply current (idd) characterist ics, igloo nano sleep mode* . 2-8 values for i cca current were updated for agln010, agln015, and agln030 in table 2-12 ? quiescent supply current (idd), no igloo nano flash*freeze mode 1 . 2-8 values for pac1 and pac2 were added to table 2-15 ? different components contributing to dynamic power consumption in igloo nano devices and table 2-17 ? different components contributing to dynamic power consumption in igloo nano devices . 2-10 , 2-11 table notes regarding wide range support were added to table 2-21 ? summary of maximum and minimum dc input and output levels . 2-19 1.2 v lvcmos wide range values were added to table 2-22 ? summary of maximum and minimum dc input levels and table 2-23 ? summary of ac measuring points . 2-19 , 2-20 the following table note was added to table 2-25 ? summary of i/o timing characteristics?software default settings and table 2-26 ? summary of i/o timing characteristics?sof tware default settings : "all lvcmos 3.3 v software macros support lvcmos 3.3 v wide r ange, as specified in the jesd8-b specification." 2-21 3.3 v lvcmos wide range and 1.2 v wide range were added to table 2-28 ? i/o output buffer maximum resistances 1 and table 2-30 ? i/o short currents iosh/iosl . 2-23 , 2-24 revision / version changes page
igloo nano low power flash fpgas revision 17 5-7 revision 1 (cont?d) the "qn48" pin diagram was revised. 4-16 packaging advance v0.2 note 2 for the "qn48" , "qn68" , and "100-pin qfn" pin diagrams was changed to "the die attach paddle of the package is tied to ground (gnd)." 4-16 , 4-19 the "vq100" pin diagram was revised to move the pin ids to the upper left corner instead of the upper right corner. 4-23 revision 0 (oct 2008) product brief advance v0.2 the following tables and sections were updated to add the uc81 and cs81 packages for agl030: "igloo nano devices" "i/os per package" "igloo nano products available in the z feature grade" "temperature grade offerings" n/a the "i/os per package" table was updated to add the following information to table note 4: "for nano devices, the vq 100 package is offered in both leaded and rohs-compliant versions. all other packages are rohs-compliant only." ii the "igloo nano products available in the z feature grade" section was updated to remove qn100 for agln250. iv the device architecture figures, figure 1-3 ? igloo device architecture overview with two i/o banks (agln060, agln125) through figure 1-4 ? igloo device architecture overview with four i/o banks (agln250) , were revised. figure 1-1 ? igloo device architecture overview with two i/o banks and no ram (agln010 and agln030) is new. 1-4 through 1-5 the "pll and ccc" section was revised to include information about ccc-gls in agln020 and smaller devices. 1-7 the "i/os with advanced i/o standards" section was revised to add information about igloo nano devices supporting double-data-rate applications. 1-8 revision / version changes page
datasheet information 5-8 revision 17 datasheet categories categories in order to provide the latest information to des igners, some datasheet parameters are published before data has been fully characterized from silicon devices. the data provided for a given device, as highlighted in the "igloo nano device status" table on page ii , is designated as either "product brief," "advance," "preliminary," or "production." the definitions of these categories are as follows: product brief the product brief is a summarized version of a data sheet (advance or producti on) and contains general product information. this document gives an overvi ew of specific device and family information. advance this version contains initial estimated information bas ed on simulation, other products, devices, or speed grades. this information can be used as estimates, bu t not for production. this label only applies to the dc and switching characteristics chapter of the da tasheet and will only be used when the data has not been fully characterized. preliminary the datasheet contains information based on simulation and/or initial characterization. the information is believed to be correct, but changes are possible. unmarked (production) this version contains information that is considered to be final. export administration regulations (ear) the products described in this document are subj ect to the export administ ration regulations (ear). they could require an approved export license prior to export from the united st ates. an export includes release of product or disclosure of technology to a foreign national inside or outside the united states. safety critical, life support, and high-reliability applications policy the microsemi products described in this advance status document may not have completed microsemi?s qualification process. microsemi may amend or enhance products during the product introduction and qualification process, resulting in ch anges in device functionality or performance. it is the responsibility of each customer to ensure the fitness of any microsemi product (but especially a new product) for a particular purpose, including approp riateness for safety-critical, life-support, and other high-reliability applications. consult microsemi?s terms and conditions for specific liability exclusions relating to life-support applications. a reliability report covering all of the microsemi soc products group?s products is at http://www.microsemi.com/s ocdocuments/ort_report.pdf . microsemi also offers a variety of enhanced qualificatio n and lot acceptance screening procedures. contact your local microsemi sales office for additional reliability information.

51700110-17/6.13 ? 2013 microsemi corporation. all rights reserved. microsemi and the microsemi logo are trademarks of microsemi corporation. all other trademarks and service marks are the property of their respective owners. microsemi corporation (nasdaq: mscc) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security ; enterprise and communications; and industrial and alternative energy markets. products incl ude high-performance, high-reliability analog and rf devices, mixed signal and rf integrated circuits, customizable socs, fpgas, and complete subsystems. microsemi is headquarter ed in aliso viejo, calif. learn more at www.microsemi.com . microsemi corporate headquarters one enterprise, aliso viejo ca 92656 usa within the usa: +1 (949) 380-6100 sales: +1 (949) 380-6136 fax: +1 (949) 215-4996

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